Integrated CMOS Gas Sensors

We present a low power gas sensor system on CMOS platform consisting of micromachined polysilicon microheater, temperature controller circuit, resistance readout circuit and SnO2 transducer film. The design criteria for different building blocks of the system is elaborated The microheaters are optimized for temperature uniformity as well as static and dynamic response. The electrical equivalent model for the microheater is derived by extracting thermal and mechanical poles through extensive laser doppler vibrometer measurements. The temperature controller and readout circuit are realized on 130nm CMOS technology The temperature controller re-uses the heater as a temperature sensor and controls the duty cycle of the waveform driving the gate of the power MOSFET which supplies heater current. The readout circuit, with subthreshold operation of the MOSFETs, is based oil resistance to time period conversion followed by frequency to digital converter Subthreshold operatin of MOSFETs coupled with sub-ranging technique, achieves ultra low power consumption with more than five orders of magnitude dynamic range RF sputtered SnO2 film is optimized for its microstructure to achive high sensitivity to sense LPG gas.

Drive current boosting of n-type tunnel FET with strained SiGe layer at source

Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade subthreshold swing and very small OFF current (IOFF), its practical application is questionable due to low ON current (ION) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60 mV/decade subthreshold swing along with a significant improvement in ION. The enhancement in ION is achieved by introducing a thin strained SiGe layer on top of the silicon source. Through 2D simulations it is observed that the device is nearly free from short channel effect (SCE) and its immunity towards drain induced barrier lowering (DIBL) increases with increasing germanium mole fraction. It is also found that the body bias does not change the drive current but after body current gets affected. An ION of View the MathML source and a minimum average subthreshold swing of 13 mV/decade is achieved for 100 nm channel length device with 1.2 V supply voltage and 0.7 Ge mole fraction, while maintaining the IOFF in fA range.

'Wet N2O oxidation' process and interface state density characterization of nanoscale nitrided SiO2 for flash memory application

In this paper we first present the 'wet N2O' furnace oxidation process to grow nitrided tunnel oxides in the thickness range 6 to 8 nm on silicon at a temperature of 800 degrees C. Electrical characteristics of MOS capacitors and MOSFETs fabricated using this oxide as gate oxide have been evaluated and the superior features of this oxide are ascertained The frequency response of the interface states, before and after subjecting the MOSFET gate oxide to constant current stress, is studied using a simple analytical model developed in this work.

Necessity for quantum mechanical simulation for the future technology nodes

In this paper we present and compare the results obtained from semi-classical and quantum mechanical simulation for a Double Gate MOSFET structure to analyze the electrostatics and carrier dynamics of this device. The geometries like gate length, body, thickness of this device have been chosen according to the ITRS specification for the different technology nodes. We have shown the extent of deviation between the semi-classical and quantum mechanical results and hence the need of quantum simulations for the promising nanoscale devices in the future technology nodes predicted in ITRS.

HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET

In this letter, we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of an HEMT and a FinFET, to obtain excellent performance and good OFF-state control. Followed by the description of the design, 3-D device simulation has been performed to predict the characteristics of the device. The device has been benchmarked against published state of the art HEMT as well as planar and nonplanar Si n-MOSFET data of comparable gate length using standard benchmarking techniques.

Ellipsometry as a Sensitive Technique to Probe film -Substrate Interfaces: Al2O3 on Si(100)

An attempt has been made to study the film-substrate interface by using a sensitive, non- conventional tool. Because of the prospective use of gate oxide in MOSFET devices, we have chosen to study alumina films grown on silicon. Film-substrate interface of alumina grown by MOCVD on Si(100) was studied systematically using spectroscopic ellipsometry in the range 1.5-5.0 eV, supported by cross-sectional SEM, and SIMS. The (ε1,ε2) versus energy data obtained for films grown at 600°C, 700°C, and 750°C were modeled to fit a substrate/interface/film “sandwich”. The experimental results reveal (as may be expected) that the nature of the substrate -film interface depends strongly on the growth temperature. The simulated (ε1,ε2) patterns are in excellent agreement with observed ellipsometric data. The MOCVD precursors results the presence of carbon in the films. Theoretical simulation was able to account for the ellipsometry data by invoking the presence of “free” carbon in the alumina films.

Electron Cyclotron Resonance in Strained Si and Si0.94Ge0.06 Channels on Relaxed Si0.62Ge0.38 Buffers Grown by Rapid Thermal Chemical Vapor Deposition

We report the far-infrared measurements of the electron cyclotron resonance absorption in n-type Si/Si0. 62Ge0.38 and Si0.94Ge0.06 /Si0. 62Ge0.38 modulation- doped heterostructures grown by rapid thermal chemical vapor deposition. The strained Si and Si0.94Ge0.06 channels were grown on relaxed Si0.62Ge0.38 buffer layers, which consist of 0.6 μm uniform Si0.62Ge0.38 layers and 0.5 μm compositionally graded relaxed SiGe layers from 0% Ge to 38 % Ge. The buffer layers were annealed at 800 °C for 1 hr to obtain complete relaxation. The samples had 100 Å spacers and 300 Å 2×1019 cm-3 n-type supply layers on the tops of the 75 Å channels. The far-infrared measurements of electron cyclotron resonance were performed at 4K with the magnetic field of 4 – 8 Tesla. The effective masses determined from the slope of center frequency of absorption peak vs applied magnetic field plot are 0.20 mo and 0.19 mo for the two dimensional electron gases in the Si and Si0.94Ge0.06 channels, respectively. The Si effective mass is very close to that of two dimensional electron gas in Si MOSFET (0.198mo). The electron effective mass of Si0.94Ge0.06 is reported for the first time and about 5 % lower than that of pure Si.

Necessity for quatum simulation for future technology nodes

In this paper we present and compare the results obtained from semi-classical and quantum mechanical simulation for a double gate MOSFET structure to analyze the electrostatics and carrier dynamics of this device. The geometries like gate length, body thickness of this device have been chosen according to the ITRS specification for the different technology nodes. We have shown the extent of deviation between the semi- classical and quantum mechanical results and hence the need of quantum simulations for the promising nanoscale devices in the future technology nodes predicted in ITRS.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

Multilevel inverters for low-power application

Multilevel inverters are an attractive solution in the medium-voltage and high-power applications. However in the low-power range also it can be a better solution compared to two-level inverters, if MOSFETs are used as devices switching in the order of 100 kHz. The effect of clamping diodes in the diode-clamped multilevel inverters play an important role in determining its efficiency. Power loss introduced by the reverse recovery of MOSFET body diode prohibits the use of MOSFET in hard-switched inverter legs. A technique of avoiding reverse recovery loss of MOSFET body diode in a three-level neutral point clamped inverter is suggested. The use of multilevel inverters topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps in reducing the size of the inverter. This study elaborates the trade-off analysis to quantify the suitability of multilevel inverters in the low-power applications. Advantages of using a MOSFET-based three-level diode-clamped inverter for a PM motor drive and UPS systems are discussed.

Underlap Optimization in HFinFET in Presence of Interface Traps

In this work, using 3-D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the ON-OFF ratio as well as the subthreshold characteristics in an ultrashort channel n-type device without significantON performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be promising when compared against ITRS 2009 performance projections, as well as published state of the art planar and nonplanar Silicon MOSFET data of comparable gate lengths using standard benchmarking techniques.

Signal-Powered Low-Drop-Diode Equivalent Circuit for Full-Wave Bridge Rectifier

Piezoelectric-device-based vibration energy harvesting requires a rectifier for conversion of input ac to usable dc form. Power loss due to diode drop in rectifier is a significant fraction of the already low levels of harvested power. The proposed circuit is a low-drop-diode equivalent, which mimics a diode using linear region-operated MOSFET. The proposed diode equivalent is powered directly from input signal and requires no additional power supply for its control. Power used by the control circuit is kept at a bare minimum to have an overall output power improvement. Diode equivalent was used to replace the four diodes in a full-wave bridge rectifier, which is the basic full- wave rectifier and is a part of the more advanced rectifiers like switch-only and bias-flip rectifiers. Simulation in 130-nm technology and experiment with discrete components show that a bridge rectifier with the proposed diode provides a 30-169% increase in output power extracted from piezoelectric device, as compared to a bridge rectifier with diode-connected MOSFETs. The bridge rectifier with the proposed diode can extract 90% of the maximum available power from an ideal piezoelectric device-bridge rectifier circuit. Setting aside the constraint of power loss, simulations indicate that diode drop as low as 10 mV at 38 mu A can be achieved.

Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (V-T) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (phi(s)) to a value phi(sT) necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that phi(sT). The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3 x 10(-15)-5 x 10(17)/cm(3). Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature. (C) 2012 Elsevier B.V. All rights reserved.

Graphene transistors for CMOS applications: opportunities and challenges

In the last decade, there has been a tremendous interest in Graphene transistors. The greatest advantage for CMOS nanoelectronics applications is the fact that Graphene is compatible with planar CMOS technology and potentially offers excellent short channel properties. Because of the zero bandgap, it will not be possible to turn off the MOSFET efficiently and hence the typical on current to off current ratio (Ion/Ioff) has been less than 10. Several techniques have been proposed to open the bandgap in Graphene. It has been demonstrated, both theoretically and experimentally, that Graphene Nanoribbons (GNR) show a bandgap which is inversely proportional to their width. GNRs with about 20 nm width have bandgaps in the range of 100meV. But it is very difficult to obtain GNRs with well defined edges. An alternate technique to open the band gap is to use bilayer Graphene (BLG), with an asymmetric bias applied in the direction perpendicular to their plane. Another important CMOS metric, the subthreshold slope is also limited by the inability to turn off the transistor. However, these devices could be attractive for RF CMOS applications. But even for analog and RF applications the non-saturating behavior of the drain current can be an issue. Although some studies have reported current saturation, the mechanisms are still not very clear. In this talk we present some of our recent findings, based on simulations and experiments, and propose possible solutions to obtain high on current to off current ratio. A detailed study on high field transport in grapheme transistors, relevant for analog and RF applications will also be presented.

Device oriented statistical modeling method for process variability in 45nm analog CMOS technology

With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.