Low-cutting devices for harvesting corn /

"August, 1929."

A multiwavelength low-power wavelength-locked slotted Fabry-Perot laser source for WDM applications

Wavelength-locking of a multiwavelength stabilized slotted Fabry-Perot (SFP) laser to a single-mode laser source is experimentally demonstrated. The SFP resonates at channels spaced by similar to 8 nm between 1510 and 1565 nm over a wide range of temperatures and drive currents. Under low-power (<- 20 dBm) external optical injection, wavelength-locking with a sidemode suppression ratio (SMSR) > 25 dB is achieved. A locking width of > 25 GHz and SMSR > 30 dB can be achieved for each locked wavelength channel at injection power > - 16 dBm.

Low-Power Tracking Image Sensor Based on Biological Models of Attention

This paper presents implementation of a low-power tracking CMOS image sensor based on biological models of attention. The presented imager allows tracking of up to N salient targets in the field of view. Employing "smart" image sensor architecture, where all image processing is implemented on the sensor focal plane, the proposed imager allows reduction of the amount of data transmitted from the sensor array to external processing units and thus provides real time operation. The imager operation and architecture are based on the models taken from biological systems, where data sensed by many millions of receptors should be transmitted and processed in real time. The imager architecture is optimized to achieve low-power dissipation both in acquisition and tracking modes of operation. The tracking concept is presented, the system architecture is shown and the circuits description is discussed.

Design of a low power - high temperature heated ceramic sensor to detect halogen gases

The design, construction and optimization of a low power-high temperature heated ceramic sensor to detect leaking of halogen gases in refrigeration systems are presented. The manufacturing process was done with microelectronic assembly and the Low Temperature Cofire Ceramic (LTCC) technique. Four basic sensor materials were fabricated and tested: Li2SiO3, Na2SiO3, K2SiO3, and CaSiO 3. The evaluation of the sensor material, sensor size, operating temperature, bias voltage, electrodes size, firing temperature, gas flow, and sensor life was done. All sensors responded to the gas showing stability and reproducibility. Before exposing the sensor to the gas, the sensor was modeled like a resistor in series and the calculations obtained were in agreement with the experimental values. The sensor response to the gas was divided in surface diffusion and bulk diffusion; both were analyzed showing agreement between the calculations and the experimental values. The sensor with 51.5%CaSiO3 + 48.5%Li 2SiO3 shows the best results, including a stable current and response to the gas. ^

Design of a Low Power – High Temperature Heated Ceramic Sensor to Detect Halogen Gases

The design, construction and optimization of a low power-high temperature heated ceramic sensor to detect leaking of halogen gases in refrigeration systems are presented. The manufacturing process was done with microelectronic assembly and the Low Temperature Cofire Ceramic (LTCC) technique. Four basic sensor materials were fabricated and tested: Li2SiO3, Na2SiO3, K2SiO3, and CaSiO3. The evaluation of the sensor material, sensor size, operating temperature, bias voltage, electrodes size, firing temperature, gas flow, and sensor life was done. All sensors responded to the gas showing stability and reproducibility. Before exposing the sensor to the gas, the sensor was modeled like a resistor in series and the calculations obtained were in agreement with the experimental values. The sensor response to the gas was divided in surface diffusion and bulk diffusion; both were analyzed showing agreement between the calculations and the experimental values. The sensor with 51.5%CaSiO3 + 48.5%Li2SiO3 shows the best results, including a stable current and response to the gas.

Controllo ultra-low power di un modulatore back-scattering per applicazioni di localizzazione in sistemi RFID

In questa tesi viene elaborata un'applicazione ultra-low power (ULP) basata su microcontrollore, per implementare la procedura di controllo di diversi circuiti di un tag RFID. Il tag preso in considerazione è pensato per lavorare in assenza di batteria, da cui la necessita' di ridurre i consumi di potenza. La sua attivazione deve essere inoltre comandata attraverso un'architettura Wake up Radio (WuR), in cui un segnale di controllo radio indirizza e attiva il circuito. Nello specifico, la rete di decodifica dell'indirizzo è stata realizzata mediante il modulo di comunicazione seriale del microcontrollore. Nel Capitolo 1 verrà introdotto il tema dell'Energy Harvesting. Nel Capitolo 2 verrà illustrata l'architettura del sistema nel suo complesso. Nel Capitolo 3 verrà spiegato dettagliatamente il funzionamento del microcontrollore scelto. Il Capitolo 4 sarà dedicato al firmware implementato per svolgere le operazioni fondamentali imputate al micro per i compiti di controllo. Verrà inoltre introdotto il codice VHDL sviluppato per emulare l'output del modulo WuR mediante un FPGA della famiglia Cyclone II. Nel Capitolo 5 verrà presentata una stima dei consumi del microcontrollore in funzione dei parametri di configurazione del sistema. Verrà inoltre effettuato un confronto con un altro microcontrollore che in alcune condizioni potrebbe rappresentare iun'alternativa valida di progetto. Nei Capitoli 6 e 7 saranno descritti possibili sviluppi futuri e conclusioni del progetto. Le specifiche di progetto rilevanti della tesi sono: 1. minimo consumo energetico possibile del microcontrollore ULP 2. elevata rapidità di risposta per la ricezione dei tag, per garantire la ricezione di un numero maggiore possibile di indirizzi (almeno 20 letture al secondo), in un range di tempo limitato 3. generazione di un segnale PWM a 100KHz di frequenza di commutazione con duty cycle 50% su cui basare una modulazione in back-scattering.

Designing Short Term Wave Traces to Assess Wave Power Devices

In recent years modern numerical methods have been employed in the design of Wave Energy Converters (WECs), however the high computational costs associated with their use makes it prohibitive to undertake simulations involving statistically relevant numbers of wave cycles. Experimental tests in wave tanks could also be performed more efficiently and economically if short time traces, consisting of only a few wave cycles, could be used to evaluate the hydrodynamic characteristics of a particular device or design modification. Ideally, accurate estimations of device performance could be made utilizing results obtained from investigations with a relatively small number of wave cycles. However the difficulty here is that many WECs, such as the Oscillating Wave Surge Converter (OWSC), exhibit significant non-linearity in their response. Thus it is challenging to make accurate predictions of annual energy yield for a given spectral sea state using short duration realisations of that sea. This is because the non-linear device response to particular phase couplings of sinusoidal components within those time traces might influence the estimate of mean power capture obtained. As a result it is generally accepted that the most appropriate estimate of mean power capture for a sea state be obtained over many hundreds (or thousands) of wave cycles. This ensures that the potential influence of phase locking is negligible in comparison to the predictions made. In this paper, potential methods of providing reasonable estimates of relative variations in device performance using short duration sea states are introduced. The aim of the work is to establish the shortness of sea state required to provide statistically significant estimations of the mean power capture of a particular type of Wave Energy Converter. The results show that carefully selected wave traces can be used to reliably assess variations in power output due to changes in the hydrodynamic design or wave climate. 

Material characterization and process development for indium-arsenide / indium-gallium-antimonide channel, high electron mobility transistors for low power, high speed applications

Efforts to push the performance of transistors for millimeter-wave and microwave applications have borne fruit through device size scaling and the use of novel material systems. III-V semiconductors and their alloys hold a distinct advantage over silicon because they have much higher electron mobility which is a prerequisite for high frequency operation. InGaAs/InP pseudomorphic heterojunction bipolar transistors (HBTs) have demonstrated fT of 765 GHz at room temperature and InP based high electron mobility transistors (HEMTs) have demonstrated fMax of 1.2 THz. The 6.1 A lattice family of InAs, GaSb, AlSb covers a wide variety of band gaps and is an attractive future material system for high speed device development. Extremely high electron mobilities ~ 30,000 cm^2 V^-1s^-1 have been achieved in modulation doped InAs-AlSb structures. The work described in this thesis involves material characterization and process development for HEMT fabrication on this material system.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.

High performance and energy-efficient instruction cache design and optimisation for ultra-low-power multi-core clusters

High Energy efficiency and high performance are the key regiments for Internet of Things (IoT) end-nodes. Exploiting cluster of multiple programmable processors has recently emerged as a suitable solution to address this challenge. However, one of the main bottlenecks for multi-core architectures is the instruction cache. While private caches fall into data replication and wasting area, fully shared caches lack scalability and form a bottleneck for the operating frequency. Hence we propose a hybrid solution where a larger shared cache (L1.5) is shared by multiple cores connected through a low-latency interconnect to small private caches (L1). However, it is still limited by large capacity miss with a small L1. Thus, we propose a sequential prefetch from L1 to L1.5 to improve the performance with little area overhead. Moreover, to cut the critical path for better timing, we optimized the core instruction fetch stage with non-blocking transfer by adopting a 4 x 32-bit ring buffer FIFO and adding a pipeline for the conditional branch. We present a detailed comparison of different instruction cache architectures' performance and energy efficiency recently proposed for Parallel Ultra-Low-Power clusters. On average, when executing a set of real-life IoT applications, our two-level cache improves the performance by up to 20% and loses 7% energy efficiency with respect to the private cache. Compared to a shared cache system, it improves performance by up to 17% and keeps the same energy efficiency. In the end, up to 20% timing (maximum frequency) improvement and software control enable the two-level instruction cache with prefetch adapt to various battery-powered usage cases to balance high performance and energy efficiency.

Embedding Video Object Detection Capabilities on Low-Power Nano-Drones

Our objective for this thesis work was the deployment of a Neural Network based approach for video object detection on board a nano-drone. Furthermore, we have studied some possible extensions to exploit the temporal nature of videos to improve the detection capabilities of our algorithm. For our project, we have utilized the Mobilenetv2/v3SSDLite due to their limited computational and memory requirements. We have trained our networks on the IMAGENET VID 2015 dataset and to deploy it onto the nano-drone we have used the NNtool and Autotiler tools by GreenWaves. To exploit the temporal nature of video data we have tried different approaches: the introduction of an LSTM based convolutional layer in our architecture, the introduction of a Kalman filter based tracker as a postprocessing step to augment the results of our base architecture. We have obtain a total improvement in our performances of about 2.5 mAP with the Kalman filter based method(BYTE). Our detector run on a microcontroller class processor on board the nano-drone at 1.63 fps.

Motor Unit Spike Trains Recontruction from sEMG Signals for Gesture Classification on a Low-Power Processing Platform

Hand gesture recognition based on surface electromyography (sEMG) signals is a promising approach for the development of intuitive human-machine interfaces (HMIs) in domains such as robotics and prosthetics. The sEMG signal arises from the muscles' electrical activity, and can thus be used to recognize hand gestures. The decoding from sEMG signals to actual control signals is non-trivial; typically, control systems map sEMG patterns into a set of gestures using machine learning, failing to incorporate any physiological insight. This master thesis aims at developing a bio-inspired hand gesture recognition system based on neuromuscular spike extraction rather than on simple pattern recognition. The system relies on a decomposition algorithm based on independent component analysis (ICA) that decomposes the sEMG signal into its constituent motor unit spike trains, which are then forwarded to a machine learning classifier. Since ICA does not guarantee a consistent motor unit ordering across different sessions, 3 approaches are proposed: 2 ordering criteria based on firing rate and negative entropy, and a re-calibration approach that allows the decomposition model to retain information about previous sessions. Using a multilayer perceptron (MLP), the latter approach results in an accuracy up to 99.4% in a 1-subject, 1-degree of freedom scenario. Afterwards, the decomposition and classification pipeline for inference is parallelized and profiled on the PULP platform, achieving a latency < 50 ms and an energy consumption < 1 mJ. Both the classification models tested (a support vector machine and a lightweight MLP) yielded an accuracy > 92% in a 1-subject, 5-classes (4 gestures and rest) scenario. These results prove that the proposed system is suitable for real-time execution on embedded platforms and also capable of matching the accuracy of state-of-the-art approaches, while also giving some physiological insight on the neuromuscular spikes underlying the sEMG.