Predicting the relationship between reliability and geometric parameters of cu column bumped flip-chips

Cu column bumping is a novel flip chip packaging technique that allows Cu columns to be bonded directly with the dies. It has eliminated the under-bump-metallurgy (UBM) fonnation step of the traditional flip chip manufacturing process. This bumping technique has the potential benefits of simplifying the flip chip manufacturing process, increasing productivity and the UO counts. In this paper, a study of reliability of Cu column bumped flip chips will be presented. Computer modelling methods have been used to predict the shape of solder joints and the response of flip chips to cyclic thermal-mechanical loading. The accumulated plastic strain energy at the corner solder joints has been used as an indicator of the solder joint reliability. Models with a wide range of design parameters have been compared for their reliability. The design parameters that have been investigated are the copper column height and radius, PCB pad radius, solder volume and Cu column wetting height. The relative importance ranking of these parameters has been obtained. The Lead-free solder material 96.5Sn3.5Ag has been used in this modelling work.

Stencil printing at sub-100 microns pitch

This article presents the latest print results at less than 100 microns pitch obtained in stencil printing type 6 and 7 lead-free solder pastes and conductive adhesives. The advantages of the microengineered stencil arc presented and compared with other bonding technologies. Characterisation of the print deposits is presented and future applications of stencil printing are described.

Wetting and Reaction of Sn-2.8Ag-0.5Cu-1.0Bi Solder with Cu and Ni Substrates

The wettability of newly developed Sn-2.8Ag-0.5Cu-1.0Bi lead-free solder on Cu and Ni substrates was assessed through the wetting balance tests. The wettability assessment parameters such as contact angle (ϑc) and maximum wetting force (Fw) were documented for three solder bath temperatures with three commercial fluxes, namely, no-clean (NC), nonactivated (R), and water-soluble organic acid flux (WS). It was found that the lead-free Sn-2.8Ag-0.5Cu-1.0Bi solder exhibited less wetting force, i.e., poorer wettability, than the conventional Sn-37Pb solder for all flux types and solder bath temperatures. The wettability of Sn-2.8Ag-0.5Cu-1.0Bi lead-free solder on Cu substrate was much higher than that on Ni substrate. Nonwetting for Sn-2.8Ag-0.5Cu-1.0Bi and Sn-Pb solders on Ni substrate occurred when R-type flux was used. A model was built and simulations were performed for the wetting balance test. The simulation results were found very close to the experimental results. It was also observed that larger values of immersion depth resulted in a decrease of the wetting force and corresponding meniscus height, whereas the increase in substrate perimeter enhanced the wettability. The wetting reactions between the solder and Cu/Ni substrates were also investigated, and it was found that Cu atoms diffused into the solder through the intermetallic compounds (IMCs) much faster than did the Ni atoms. Rapid formation of IMCs inhibited the wettability of Sn-2.8Ag-0.5Cu-1.0Bi solder compared to the Sn-Pb solder.

Computational modelling for reliable flip-chip packaging at sub-100 micron pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.

Decision support systems for eco-friendly electronic products

This paper discusses an optimisation based decision support system and methodology for electronic packaging and product design and development which is capable of addressing in efficient manner specified environmental, reliability and cost requirements. A study which focuses on the design of a flip-chip package is presented. Different alternatives for the design of the flip-chip package are considered based on existing options for the applied underfill and volume of solder material used to form the interconnects. Variations in these design input parameters have simultaneous effect on package aspects such as cost, environmental impact and reliability. A decision system for the design of the flip-chip that uses numerical optimisation approach is used to identify the package optimal specification which satisfies the imposed requirements. The reliability aspect of interest is the fatigue of solder joints under thermal cycling. Transient nonlinear finite element analysis (FEA) is used to simulate the thermal fatigue damage in solder joints subject to thermal cycling. Simulation results are manipulated within design of experiments and response surface modelling framework to provide numerical model for reliability which can be used to quantify the package reliability. Assessment of the environmental impact of the package materials is performed by using so called Toxic Index (TI). In this paper we demonstrate the evaluation of the environmental impact only for underfill and lead-free solder materials. This evaluation is based on the amount of material per flip-chip package. Cost is the dominant factor in contemporary flip-chip packaging industry. In the optimisation based decision support system for the design of the flip-chip package, cost of materials which varies as a result of variations in the design parameters is considered.

Optimisation modelling for design of advanced interconnects

This paper describes a computational strategy for virtual design and prototyping of electronic components and assemblies. The design process is formulated as a design optimisation problem. The solution of this problem identifies not only the design which meets certain user specified requirements but also the design with the maximum possible improvement in particular aspects such as reliability, cost, etc. The modelling approach exploits numerical techniques for computational analysis (Finite Element Analysis) integrated with numerical methods for approximation, statistical analysis and optimisation. A software framework of modules that incorporates the required numerical techniques is developed and used to carry out the design optimisation modelling of fine-pitch flip-chip lead free solder interconnects.

Comparative wetting behavior of Sn-0.7Cu and Sn-0.7Cu-0.3Ni solders on Cu and Ni substrates

Electronic packaging industries are now in great challenge to find a suitable lead-free solder as an interconnection material to replace the conventional SnPb solders. Many solders such as SnCu, SnAg, SnAgCu, SnZn, SnBi have already been proposed as the replacement but none of them has reached the physical and metallurgical properties similar to the SnPb solder. However, wetting is one of the basic problems that make the lead-free solder inferior as compared to the SnPb solder. Therefore, alloying with the help of third, fourth or fifth element is the researchers' interest to improve the wetting behavior of lead-free solders. This paper describes the comparative wetting behavior of Sn-0.7Cu and Sn-0.7Cu-0.3Ni solders on Cu and Ni substrates. Wetting balance tests were performed to assess the wetting behaviors. Three different commercial fluxes namely no-clean (NC), non-activated (R) and water soluble organic acid (WS)fluxes were used to assess the wettability for three solder bath temperatures. It was found that Sn0.7Cu-03Ni solder exhibits better wettability on Cu substrate for NC and WS fluxes whereas reverse results were found for R-type flux. In the case of Ni substrate, Sn-0.7Cu-0.3Ni solder showed better wetting behavior compared to the well-known Sn-0.7Cu solder. Among the three fluxes, R-type flux showed the worst performance. Very large contact angles were documented for both solders with this flux. Higher solder bath temperature lowered the contact angles, increased the wetting forces and enhanced the wettability. Computer modeling of wetting balance test revealed that both the wetting force and meniscus height are inversely proportional to the contact angles. Modeling results also reveal that increase in solder bath depths and radiuses do not affect significantly on the wetting behavior.

Effect of 0.5 wt % Cu addition in Sn–3.5% Ag solder on the dissolution rate of Cu metallization

The dissolution of thin film under-bump-metallization (UBM) by molten solder has been one of the most serious processing problems in electronic packaging technology. Due to a higher melting temperature and a greater Sn content, a molten lead-free solder such as eutectic SnAg has a faster dissolution rate of thin film UBM than the eutectic SnPb. The work presented in this paper focuses on the role of 0.5 wt % Cu in the base Sn–3.5%Ag solder to reduce the dissolution of the Cu bond pad in ball grid array applications. We found that after 0.5 wt % Cu addition, the rate of dissolution of Cu in the molten Sn–3.5%Ag solder slows down dramatically. Systematic experimental work was carried out to understand the dissolution behavior of Cu by the molten Sn–3.5%Ag and Sn–3.5%Ag–0.5%Cu solders at 230–250 °C, for different time periods ranging from 1 to 10 min. From the curves of consumed Cu thickness, it was concluded that 0.5 wt % Cu addition actually reduces the concentration gradient at the Cu metallization/molten solder interface which reduces the driving force of dissolution. During the dissolution, excess Cu was found to precipitate out due to heterogeneous nucleation and growth of Cu6Sn5 at the solder melt/oxide interface. In turn, more Cu can be dissolved again. This process continues with time and leads to more dissolution of Cu from the bond pad than the amount expected from the solubility limit, but it occurs at a slower rate for the molten Sn–3.5%Ag–0.5%Cu solder. © 2003 American Institute of Physics.

Reliability analysis of SiP structures

This presentation discusses latest developments in SiP technology and the challenges for design in terms of manufacture and reliability. It presents results from a UK government funded project that aims to develop modelling techniques that will assess the thermo-mechanical reliability of SiP structures such as (i) stacked die, (ii) side-by-side dies and (iii) embedded die. Finite element analysis coupled with numerical optimisation and uncertainty analysis is used is used to model the reliability of a particular package design. In particular, the damage (energy density) in the lead free solder interconnects under accelerated temperature cycling is predicted and used to observe the fatigue life-time. Warpage of the structure is also investigated

Computational approach for reliable and robust system-in-package design

A computational modelling approach integrated with optimisation and statistical methods that can aid the development of reliable and robust electronic packages and systems is presented. The design for reliability methodology is demonstrated for the design of a SiP structure. In this study the focus is on the procedure for representing the uncertainties in the package design parameters, their impact on reliability and robustness of the package design and how these can be included in the design optimisation modelling framework. The analysis of thermo-mechanical behaviour of the package is conducted using non-linear transient finite element simulations. Key system responses of interest, the fatigue life-time of the lead-free solder interconnects and warpage of the package, are predicted and used subsequently for design purposes. The design tasks are to identify the optimal SiP designs by varying several package input parameters so that the reliability and the robustness of the package are improved and in the same time specified performance criteria are also satisfied

Reliability based design optimisation for system-in-package

This paper discusses a reliability based optimisation modelling approach demonstrated for the design of a SiP structure integrated by stacking dies one upon the other. In this investigation the focus is on the strategy for handling the uncertainties in the package design inputs and their implementation into the design optimisation modelling framework. The analysis of fhermo-mechanical behaviour of the package is utilised to predict the fatigue life-time of the lead-free board level solder interconnects and warpage of the package under thermal cycling. The SiP characterisation is obtained through the exploitation of Reduced Order Models (ROM) constructed using high fidelity analysis and Design of Experiments (DoE) methods. The design task is to identify the optimal SiP design specification by varying several package input parameters so that a specified target reliability of the solder joints is achieved and in the same time design requirements and package performance criteria are met

Rheological characterisation and printing performance of Sn/Ag/Cu solder pastes

Lead-free solder paste printing process accounts for majority of the assembly defects in the electronic manufacturing industry. The study investigates rheological behaviour and stencil printing performance of the lead-free solder pastes (Sn/Ag/Cu). Oscillatory stress sweep test was carried out to study the visco-elastic behaviour of the lead-free solder pastes. The visco-elastic behaviour of the paste encompasses solid and liquid characteristic of the paste, which could be used to study the flow behaviour experienced by the pastes during the stencil printing process. From this study, it was found that the solid characteristics (G0) is higher than the liquid characteristic (G0 0) for the pastes material. In addition, the results from the study showed that the solder paste with a large G0 = G0 0 has a higher cohesiveness resulting in poor withdrawal of the paste during the stencil printing process. The phase angles (d) was used to correlate the quality of the dense suspensions to the formulation of solder paste materials. This study has revealed the value of having a rheological measurement for explaining and characterising solder pastes for stencil printing. As the demand for lead free pastes increases rheological measurements can assist with the formulation or development of new pastes.

Rheological characterisation of solder pastes and isotropic conductive adhesives used for flip-chip assembly

Solder pastes and isotropic conductive adhesives (ICAs) are widely used as a principal bonding medium in the electronic industry. This study investigates the rheological behaviour of the pastes (solder paste and isotropic conductive adhesives) used for flip-chip assembly. Oscillatory stress sweep test are performed to evaluate solid characteristic and cohesiveness of the lead-free solder pastes and isotropic conductive adhesive paste materials. The results show that the G' (storage modulus) is higher than G '' (loss modulus) for the pastes material indicating a solid like behaviour. It result shows that the linear visco-elastic region for the pastes lies in a very small stress range, below 10 Pa. in addition, the stress at which the value of storage modulus is equal to that of loss modulus can be used as an indicator of the paste cohesiveness. The measured cross-over stress at G'=G '' shows that the solder paste has higher stress at G'=G '' compared to conductive adhesives. Creep-recovery test method is used to study the slump behaviour in the paste materials. The conductive adhesive paste shows a good recovery when compared to the solder pastes. (C) 2008 Elsevier B.V. All rights reserved.

Wall-slip effects in SnAgCu solder pastes used in electronics assembly applications

Solder paste is the most important strategic bonding material used in the assembly of surface mount components in electronics manufacturing. As the trend towards miniaturisation of electronic products continues, there is an increasing demand for better understanding of the flow and deformation that is, the rheological behaviour of solder paste formulations. Wall slip plays an important role in characterising the flow behaviour of solder paste materials. The problem of wall slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. In rheological measurements, slip effects can generally be avoided by using roughened surfaces for measuring geometries. In this paper, a novel technique is developed to study the effect of wall slip in the rheological measurements of lead-free solder paste. The viscosity and oscillatory data obtained for three different solder paste samples (from measuring geometries of different surface roughness) havebeen analysed and compared. In viscosity measurements, slip effects were dominant at low shear rates and the use of serrated surfaces was found to be quite effective in minimizing slip effects. Oscillatory measurements were also affected by roughening the surfaces of measuring geometries.

Investigation of wall-slip effect on paste release characteristic in flip-chip stencil printing process

As the trend toward further miniaturisation of pocket and handheld consumer electronic products continues apace, the requirements for even smaller solder joints will continue. With further reductions in the size of solder joints, the reliability of solder joints will become more and more critical to the long-term performance of electronic products. Solder joints play an important role in electronics packaging, serving both as electrical interconnections between the components and the board, and as mechanical support for components. With world-wide legislation for the removal/reduction of lead and other hazardous materials from electrical and electronic products, the electronics manufacturing industry has been faced with an urgent search for new lead-free solder alloy systems and other solder alternatives. In order to achieve high volume, low cost production, the stencil printing process and subsequent wafer bumping of solder paste has become indispensable. There is wide agreement in industry that the paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on printing performance. The printing of ICAs and lead-free solder pastes through the very small stencil apertures required for flip chip applications was expected to result in increased stencil clogging and incomplete transfer of paste to the printed circuit pads. Paste release from the stencil apertures is dependent on the interaction between the solder paste, surface pad and aperture wall; including its shape. At these very narrow aperture sizes the paste rheology becomes crucial for consistent paste withdrawal because for smaller paste volumes surface tension effects become dominant over viscous flow. Successful aperture filling and release will greatly depend on the rheology of the paste material. Wall-slip plays an important role in characterising the flow behaviour of solder paste materials. The wall- slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. The wall slip effect can play an important role in ensuring successful paste release after the printing process. The aim of this study was to investigate the influence of the paste microstructure on slip formation for the paste materials (lead-free solder paste and isotropic conductive adhesives). The effect of surface roughness on the paste viscosity was investigated. It was also found that altering the surface roughness of the parallel plate measuring geometry did not significantly eliminate wall slip as was expected. But results indicate that the use of a relatively rough surface helps to increase paste adhesion to the plates, inducing structural breakdown of the paste. Most importantly, the study also demonstrated on how the wall slip formation in the paste material could be utilised for understanding of the paste microstructure and its flow behaviour