Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Characteristics of j.f.e.t.s. taking the separation of gate electrode from the source and drain electrodes into account

The performance characteristics of a junction field-effect transistor (j.f.e.t.) are evaluated considering the presence of the gap between the gate electrode and the source and drain terminals. It is concluded that the effect of the gap is to demand a higher drain voltage to maintain the same drain current. So long as the device is operated at the same drain current, the presence of the gap does not change the performance of the device as an amplifier. The nature of the performance of the device as a variable resistor is not affected by the gap if it is less than or equal to the physical height of the channel. For gap lengths larger than the channel height, the effect of the gap is to add a series resistance in the drain.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Simulation of Potential and Electric Field Profiles for transmission line Insulators

Since the end of second world war, extra high voltage ac transmission has seen its development. The distances between generating and load centres as well as the amount of power to be handled increased tremendously for last 50 years. The highest commercial voltage has increased to 765 kV in India and 1,200 kV in many other countries. The bulk power transmission has been mostly performed by overhead transmission lines. The dual task of mechanically supporting and electrically isolating the live phase conductors from the support tower is performed by string insulators. Whether in clean condition or under polluted conditions, the electrical stress distribution along the insulators governs the possible flashover, which is quite detrimental to the system. Hence the present investigation aims to study accurately, the field distribution for various types of porcelain/ceramic insulators (Normal and Antifog discs) used for high-voltage transmission. The surface charge simulation method is employed for the field computation. A comparison on normalised surface resistance, which is an indicator for the stress concentration under polluted condition, is also attempted.

Simulation of surface and volume stress for high voltage transmission insulators

The bulk of power transmission from the generating stations to the load centres is carried through overhead lines. The distances involved could span several hundreds of kilometres. To minimize line losses, power transmission over such long distances is carried out at high voltages (several hundreds of kV). A network of outdoor lines operating at different voltages has been found to be the most economical method of power delivery. The disc insulators perform dual task of mechanically supporting and electrically isolating the live phase conductors from the support tower. These insulators have to perform under various environmental conditions; hence the electrical stress distribution along the insulators governs the possible flashover, which is quite detrimental to the system. In view of this the present investigation aims to simulate the surface electric field stress on different types of porcelain/ceramic insulators; both normal and anti-fog type discs which are used for high voltage transmission/distribution systems are considered. The surface charge simulation method is employed for the field computation to simulate potential, electric field, surface and bulk/volume stress.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Junction between surfaces of two topological insulators

We study the properties of a line junction which separates the surfaces of two three-dimensional topological insulators. The velocities of the Dirac electrons on the two surfaces may be unequal and may even have opposite signs. For a time-reversal invariant system, we show that the line junction is characterized by an arbitrary parameter alpha which determines the scattering from the junction. If the surface velocities have the same sign, we show that there can be edge states which propagate along the line junction with a velocity and spin orientation which depend on alpha and the ratio of the velocities. Next, we study what happens if the two surfaces are at an angle phi with respect to each other. We study the scattering and differential conductance through the line junction as functions of phi and alpha. We also find that there are edge states which propagate along the line junction with a velocity and spin orientation which depend on phi. Finally, if the surface velocities have opposite signs, we find that the electrons must transmit into the two-dimensional interface separating the two topological insulators.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Performance and variability trade-off with gate-to-source/drain overlap length

The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

Substrate temperature influenced physical properties of silicon MOS devices with TiO2 gate dielectric

DC reactive magnetron sputtering technique was employed for deposition of titanium dioxide (TiO2) films. The films were formed on Corning glass and p-Si (100) substrates by sputtering of titanium target in an oxygen partial pressure of 6x10-2 Pa and at different substrate temperatures in the range 303 673 K. The films formed at 303 K were X-ray amorphous whereas those deposited at substrate temperatures?=?473 K were transformed into polycrystalline nature with anatase phase of TiO2. Fourier transform infrared spectroscopic studies confirmed the presence of characteristic bonding configuration of TiO2. The surface morphology of the films was significantly influenced by the substrate temperature. MOS capacitor with Al/TiO2/p-Si sandwich structure was fabricated and performed currentvoltage and capacitancevoltage characteristics. At an applied gate voltage of 1.5 V, the leakage current density of the device decreased from 1.8?x?10-6 to 5.4?x?10-8 A/cm2 with the increase of substrate temperature from 303 to 673 K. The electrical conduction in the MOS structure was more predominant with Schottky emission and Fowler-Nordheim conduction. The dielectric constant (at 1 MHz) of the films increased from 6 to 20 with increase of substrate temperature. The optical band gap of the films increased from 3.50 to 3.56 eV and refractive index from 2.20 to 2.37 with the increase of substrate temperature from 303 to 673 K. Copyright (c) 2012 John Wiley & Sons, Ltd.

Continuum theory of edge states of topological insulators: variational principle and boundary conditions

We develop a continuum theory to model low energy excitations of a generic four-band time reversal invariant electronic system with boundaries. We propose a variational energy functional for the wavefunctions which allows us to derive natural boundary conditions valid for such systems. Our formulation is particularly suited for developing a continuum theory of the protected edge/surface excitations of topological insulators both in two and three dimensions. By a detailed comparison of our analytical formulation with tight binding calculations of ribbons of topological insulators modelled by the Bernevig-Hughes-Zhang (BHZ) Hamiltonian, we show that the continuum theory with a natural boundary condition provides an appropriate description of the low energy physics.

Potential and electric field distribution in a ceramic disc insulator string with faulty insulators

Ceramic/Porcelain suspension disc insulators are widely used in power systems to provide electrical insulation and mechanically support for high-voltage transmission lines. These insulators are subjected to a variety of stresses, including mechanical, electrical and environmental. These stresses act in unison. The exact nature and magnitude of these stresses vary significantly and depends on insulator design, application and its location. Due to various reasons the insulator disc can lose its electrical insulation properties without any noticeable mechanical failure. Such a condition while difficult to recognize, can enhance the stress on remaining healthy insulator discs in the string further may lead to a flashover. To understand the stress enhancement due to faulty discs in a string, attempt has been made to simulate the potential and electric field profiles for various disc insulators presently used in the country. The results of potential and electric filed stress obtained for normal and strings with faulty insulator discs are presented.