An in-depth analysis of real and perceived barriers to speech and language program participation for children with speech and language delays : a question of barriers to service?

The current study investigated the effects that barriers (both real and perceived) had on participation and completion of speech and language programs for preschool children with communication delays. I compared 36 families of preschool children with an identified communication delay that have completed services (completers) to 13 families that have not completed services (non-completers) prescribed by Speech and Language professionals. Data findings reported were drawn from an interview with the mother, a speech and language assessment of the child, and an extensive package of measures completed by the mother. Children ranged in age from 32 to 71 mos. These data were collected as part of a project funded by the Canadian Language and Literacy Research Networks of Centres of Excellence. Findings suggest that completers and non-completers shared commonalities in a number of parenting characteristics but differed significantly in two areas. Mothers in the noncompleting group were more permissive and had lower maternal education than mothers in the completing families. From a systemic standpoint, families also differed in the number of perceived barriers to treatment experienced during their time with Speech Services Niagara. Mothers in the non-completing group experienced more perceived barriers to treatment than completing mothers. Specifically, these mothers perceived more stressors and obstacles that competed with treatment, perceived more treatment demands and they perceived the relevance of treatment as less important than the completing group. Despite this, the findings suggest that non-completing families were 100% satisfied with services. Contrary to predictions, there were no significant differences in child characterisfics and economic characteristics between completers and non-completers. The findings in this study are considered exploratory and tentative due to the small sample size.

Vitamine K et fonctions cognitives chez la personne âgée en santé : une approche épidémiologique nutritionnelle

La vitamine K fait l’objet d’un intérêt croissant en regard du rôle qu’elle peut jouer dans la santé humaine hormis celui bien établi dans la coagulation sanguine. De plus en plus d’études expérimentales lui confèrent des fonctions dans le système nerveux central, particulièrement dans la synthèse des sphingolipides, l’activation de la protéine vitamine K-dépendante Gas6 et la protection contre les dommages oxydatifs. Toutefois, il demeure beaucoup moins bien établi si la perturbation de ces fonctions peut conduire à des déficits cognitifs. L’objectif principal de cette thèse est de vérifier l’hypothèse selon laquelle le statut vitaminique K des personnes âgées en santé est un déterminant de la performance cognitive. En vue de la réalisation de cet objectif, une meilleure compréhension des indicateurs du statut vitaminique K s’avérait nécessaire. Chacune des études présentées vise donc un objectif spécifique : 1) évaluer le nombre de rappels alimentaires de 24 heures non consécutifs nécessaire pour mesurer l’apport habituel de vitamine K des personnes âgées; 2) évaluer la valeur d’une seule mesure de la concentration sérique de vitamine K comme marqueur de l’exposition à long terme; et 3) examiner l’association entre le statut vitaminique K et la performance cognitive des personnes âgées en santé de la cohorte québécoise NuAge. Trois dimensions cognitives ont été évaluées soient la mémoire épisodique verbale et non-verbale, les fonctions exécutives et la vitesse de traitement de l’information. Cette thèse présente la première étude appuyant l’hypothèse d’un rôle de la vitamine K dans la cognition chez les personnes âgées. Spécifiquement, la concentration sérique de vitamine K a été associée positivement à la performance en mémoire épisodique verbale, et plus particulièrement au processus de consolidation de la trace mnésique. En accord avec les travaux chez l’animal et l’action de la protéine Gas6 dans l’hippocampe, un rôle spécifique de la vitamine K à l’étape de consolidation est biologiquement plausible. Aucune association significative n’a été observée avec les fonctions exécutives et la vitesse de traitement de l’information. Parallèlement, il a été démontré qu’une mesure unique de la concentration sérique de vitamine K constitue une mesure adéquate de l’exposition à long terme à la vitamine K. De même, il a été établi que six à 13 rappels alimentaires de 24 heures sont nécessaires pour estimer précisément l’apport de vitamine K des personnes âgées en santé. Collectivement, les résultats de ces deux études fournissent des informations précieuses aux chercheurs permettant une meilleure interprétation des études existantes et une meilleure planification des études futures. Les résultats de cette thèse constituent une avancée importante dans la compréhension du rôle potentiel de la vitamine K dans le système nerveux central et renforce la nécessité qu’elle soit considérée en tant que facteur nutritionnel du vieillissement cognitif, en particulier chez les personnes traitées par un antagoniste de la vitamine K.

Skript Interprozesskommunikation

Das hier frei verfügbare Skript gehört zu einer gleichnamigen Vorlesung, die von Prof. Dr. Lutz Wegner bis zum Sommersemester 2007 gehalten wurde. Davor lief sie bis 1999 unter dem etwas irreführenden Titel „Ausgewählte Themen zu Rechnernetzen“. Behandelt wird die IPC in UNIX-basierten Rechnernetzen. Dazu gehören allgemeine Kenntnisse der Prozessumgebung, die fork- und exec-Systemaufrufe, Lock Files, Signale, Pipes, das Botschaftenkonzept (message queues), Semaphore, Shared Memory, Remote Procedure Calls, Sockets und Threads. Jedes Konzept wird mit kleinen Beispielen besprochen, die in C geschrieben sind. Der Quelltext liegt auf unseren Anlagen vor (für AIX, LINUX, Solaris). Grundlage der Vorlesung und des Skripts ist das ausgezeichnete Buch von John Shapley Gray „Interprocess Communications in UNIX“ aus dem Jahr 1998 bzw. die auf Linux angepasste Auflage desselben Buches „Interprocess Communications in LINUX“ aus dem Jahr 2003.

Thread Scheduling Mechanisms for Multiple-Context Parallel Processors

Scheduling tasks to efficiently use the available processor resources is crucial to minimizing the runtime of applications on shared-memory parallel processors. One factor that contributes to poor processor utilization is the idle time caused by long latency operations, such as remote memory references or processor synchronization operations. One way of tolerating this latency is to use a processor with multiple hardware contexts that can rapidly switch to executing another thread of computation whenever a long latency operation occurs, thus increasing processor utilization by overlapping computation with communication. Although multiple contexts are effective for tolerating latency, this effectiveness can be limited by memory and network bandwidth, by cache interference effects among the multiple contexts, and by critical tasks sharing processor resources with less critical tasks. This thesis presents techniques that increase the effectiveness of multiple contexts by intelligently scheduling threads to make more efficient use of processor pipeline, bandwidth, and cache resources. This thesis proposes thread prioritization as a fundamental mechanism for directing the thread schedule on a multiple-context processor. A priority is assigned to each thread either statically or dynamically and is used by the thread scheduler to decide which threads to load in the contexts, and to decide which context to switch to on a context switch. We develop a multiple-context model that integrates both cache and network effects, and shows how thread prioritization can both maintain high processor utilization, and limit increases in critical path runtime caused by multithreading. The model also shows that in order to be effective in bandwidth limited applications, thread prioritization must be extended to prioritize memory requests. We show how simple hardware can prioritize the running of threads in the multiple contexts, and the issuing of requests to both the local memory and the network. Simulation experiments show how thread prioritization is used in a variety of applications. Thread prioritization can improve the performance of synchronization primitives by minimizing the number of processor cycles wasted in spinning and devoting more cycles to critical threads. Thread prioritization can be used in combination with other techniques to improve cache performance and minimize cache interference between different working sets in the cache. For applications that are critical path limited, thread prioritization can improve performance by allowing processor resources to be devoted preferentially to critical threads. These experimental results show that thread prioritization is a mechanism that can be used to implement a wide range of scheduling policies.

Análise de desempenho da rede neural artificial do tipo multilayer perceptron na era multicore

Artificial neural networks are usually applied to solve complex problems. In problems with more complexity, by increasing the number of layers and neurons, it is possible to achieve greater functional efficiency. Nevertheless, this leads to a greater computational effort. The response time is an important factor in the decision to use neural networks in some systems. Many argue that the computational cost is higher in the training period. However, this phase is held only once. Once the network trained, it is necessary to use the existing computational resources efficiently. In the multicore era, the problem boils down to efficient use of all available processing cores. However, it is necessary to consider the overhead of parallel computing. In this sense, this paper proposes a modular structure that proved to be more suitable for parallel implementations. It is proposed to parallelize the feedforward process of an RNA-type MLP, implemented with OpenMP on a shared memory computer architecture. The research consistes on testing and analizing execution times. Speedup, efficiency and parallel scalability are analyzed. In the proposed approach, by reducing the number of connections between remote neurons, the response time of the network decreases and, consequently, so does the total execution time. The time required for communication and synchronization is directly linked to the number of remote neurons in the network, and so it is necessary to investigate which one is the best distribution of remote connections

Implementação paralela escalável e eficiente do algoritmo simplex padrão em arquitetura multicore

This work presents a scalable and efficient parallel implementation of the Standard Simplex algorithm in the multicore architecture to solve large scale linear programming problems. We present a general scheme explaining how each step of the standard Simplex algorithm was parallelized, indicating some important points of the parallel implementation. Performance analysis were conducted by comparing the sequential time using the Simplex tableau and the Simplex of the CPLEXR IBM. The experiments were executed on a shared memory machine with 24 cores. The scalability analysis was performed with problems of different dimensions, finding evidence that our parallel standard Simplex algorithm has a better parallel efficiency for problems with more variables than constraints. In comparison with CPLEXR , the proposed parallel algorithm achieved a efficiency of up to 16 times better

A influência da prática meditativa sobre parâmetros psicofisiológicos e tarefas de memória operacional em indivíduos saudáveis

Meditation is described as a method for improving attention and promoting psychological and emotional stability, presenting favourable results on memory and stress tolerance as well. Studies have shown differences in physiological and psychological measurements between meditators and non-meditators. The aim of this study was to investigate the influence of regular meditation practice on working memory, psychological measurements and quality of life of healthy practitioners. We carried out a comparative study with meditators and non-meditators. Working memory tests and standard inventories of life quality, anxiety, mood, sleep quality, depression and stress were applied. Our study showed that meditators presented better scores in parameters indicative of life quality, mood, depression and stress when compared with non-meditators. Moreover, there was a trend in best performance of meditators in memory tasks (forward digit span task and Hanoi tower). These findings corroborate other studies showing that regular meditation can provide an improvement in general quality of life and affecting positively the behavioral and attentional functions in individuals

High resolution ultra high pressure liquid chromatography-time-of-flight mass spectrometry dereplication strategy for the metabolite profiling of Brazilian Lippia species

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Escalonamento de tarefas em sistemas distribuídos baseado no conceito de propriedade distribuída

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Reparação tecidual pulpar sob ação bioestimuladora do laser de baixa intensidade (LILT), e do diodo emissor de luz (LED): estudo em macacos prego

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Influência da dentina bovina e do dispositivo de microtração na resistência de união de sistemas adesivos

Pós-graduação em Odontologia Restauradora - ICT

Shedding light on the role of the prokaryotic assemblage in the biogeochemical cycles of the dark ocean

Se han eliminado las páginas en blanco

Paralelización de un algoritmo de ray tracing para arrays de mililentes

Máster Universitario en Sistemas Inteligentes y Aplicaciones Numéricas en Ingeniería (SIANI)

Performance evaluation of a parallel algorithm for simultaneous untangling and smoothing of tetrahedral meshes

[EN]A new parallel algorithm for simultaneous untangling and smoothing of tetrahedral meshes is proposed in this paper. We provide a detailed analysis of its performance on shared-memory many-core computer architectures. This performance analysis includes the evaluation of execution time, parallel scalability, load balancing, and parallelism bottlenecks. Additionally, we compare the impact of three previously published graph coloring procedures on the performance of our parallel algorithm. We use six benchmark meshes with a wide range of sizes. Using these experimental data sets, we describe the behavior of the parallel algorithm for different data sizes. We demonstrate that this algorithm is highly scalable when it runs on two different high-performance many-core computers with up to 128 processors...

Design and Performance Evaluation of Network-on-Chip Communication Protocols and Architectures

The scale down of transistor technology allows microelectronics manufacturers such as Intel and IBM to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are becoming obsolete as they struggle to sustain the increasing tight bandwidth and latency constraints that these systems demand. The most promising solution for the future chip interconnects are the Networks on Chip (NoC). NoCs are network composed by routers and channels used to inter- connect the different components installed on the single microchip. Examples of advanced processors based on NoC interconnects are the IBM Cell processor, composed by eight CPUs that is installed on the Sony Playstation III and the Intel Teraflops pro ject composed by 80 independent (simple) microprocessors. On chip integration is becoming popular not only in the Chip Multi Processor (CMP) research area but also in the wider and more heterogeneous world of Systems on Chip (SoC). SoC comprehend all the electronic devices that surround us such as cell-phones, smart-phones, house embedded systems, automotive systems, set-top boxes etc... SoC manufacturers such as ST Microelectronics , Samsung, Philips and also Universities such as Bologna University, M.I.T., Berkeley and more are all proposing proprietary frameworks based on NoC interconnects. These frameworks help engineers in the switch of design methodology and speed up the development of new NoC-based systems on chip. In this Thesis we propose an introduction of CMP and SoC interconnection networks. Then focusing on SoC systems we propose: • a detailed analysis based on simulation of the Spidergon NoC, a ST Microelectronics solution for SoC interconnects. The Spidergon NoC differs from many classical solutions inherited from the parallel computing world. Here we propose a detailed analysis of this NoC topology and routing algorithms. Furthermore we propose aEqualized a new routing algorithm designed to optimize the use of the resources of the network while also increasing its performance; • a methodology flow based on modified publicly available tools that combined can be used to design, model and analyze any kind of System on Chip; • a detailed analysis of a ST Microelectronics-proprietary transport-level protocol that the author of this Thesis helped developing; • a simulation-based comprehensive comparison of different network interface designs proposed by the author and the researchers at AST lab, in order to integrate shared-memory and message-passing based components on a single System on Chip; • a powerful and flexible solution to address the time closure exception issue in the design of synchronous Networks on Chip. Our solution is based on relay stations repeaters and allows to reduce the power and area demands of NoC interconnects while also reducing its buffer needs; • a solution to simplify the design of the NoC by also increasing their performance and reducing their power and area consumption. We propose to replace complex and slow virtual channel-based routers with multiple and flexible small Multi Plane ones. This solution allows us to reduce the area and power dissipation of any NoC while also increasing its performance especially when the resources are reduced. This Thesis has been written in collaboration with the Advanced System Technology laboratory in Grenoble France, and the Computer Science Department at Columbia University in the city of New York.