Aerodynamic Analysis of Cup Anemometers Performance: The Stationary Harmonic Response

The effect of cup anemometer shape parameters, such as the cups’ shape, their size, and their center rotation radius, was experimentally analyzed.This analysis was based on both the calibration constants of the transfer function and the most important harmonic termof the rotor’smovement,which due to the cup anemometer design is the third one.This harmonic analysis represents a new approach to study cup anemometer performances. The results clearly showed a good correlation between the average rotational speed of the anemometer’s rotor and the mentioned third harmonic term of its movement.

Effects of traffic loads on reinforced concrete railroad culverts

In the context of the present conference paper culverts are defined as an opening or conduit passing through an embankment usually for the purpose of conveying water or providing safe pedestrian and animal crossings under rail infrastructure. The clear opening of culverts may reach values of up to 12m however, values around 3m are encountered much more frequently. Depending on the topography, the number of culverts is about 10 times that of bridges. In spite of this, their dynamic behavior has received far less attention than that of bridges. The fundamental frequency of culverts is considerably higher than that of bridges even in the case of short span bridges. As the operational speed of modern high-speed passenger rail systems rises, higher frequencies are excited and thus more energy is encountered in frequency bands where the fundamental frequency of box culverts is located. Many research efforts have been spent on the subject of ballast instability due to bridge resonance, since it was first observed when high-speed trains were introduced to the Paris/Lyon rail line. To prevent this phenomenon from occurring, design codes establish a limit value for the vertical deck acceleration. Obviously one needs some sort of numerical model in order to estimate this acceleration level and at that point things get quite complicated. Not only acceleration but also displacement values are of interest e.g. to estimate the impact factor. According to design manuals the structural design should consider the depth of cover, trench width and condition, bedding type, backfill material, and compaction. The same applies to the numerical model however, the question is: What type of model is appropriate for this job? A 3D model including the embankment and an important part of the soil underneath the culvert is computationally very expensive and hard to justify taking into account the associated costs. Consequently, there is a clear need for simplified models and design rules in order to achieve reasonable costs. This paper will describe the results obtained from a 2D finite element model which has been calibrated by means of a 3D model and experimental data obtained at culverts that belong to the high-speed railway line that links the two towns of Segovia and Valladolid in Spain

Influence of aerodynamic characteristics of H beams on galloping stability

This paper presents the experimental study developed on a prismatic beam with H section, sometimes used in bridges as suspenders, vertical bars or decks. The purpose of this study is to understand the physical behavior of the air around this type of section, in order to reduce the aerodynamic loads, the onset speed of galloping and even to avoid it. To achieve this, a study of the influence of all geometric parameters that define the section has been developed. Previously, the most interesting configurations have been selected using a smoke flow visualization technique in the wind-tunnel, then the corresponding static aerodynamic loads were measured, completed with dynamic tests and, finally, the parameters governing the phenomenon of galloping determined.

Performance-based seismic design of a retaining wall

The design of containment walls suffering seismic loads traditionally has been realized with methods based on pseudoanalitic procedures such as Mononobe-Okabe's method, which it has led in certain occasions to insecure designs, that they have produced the ruin of many containment walls suffering the action of an earthquake. The recommendations gathered in Mononobe-Okabe's theory have been included in numerous Codes of Seismic Design. It is clear that a revision of these recommendations must be done. At present there is taking place an important review of the design methods of anti-seismic structures such as containment walls placed in an area of numerous earthquakes, by means of the introduction at the beginning of the decade of 1990 the Displacement Response Spectrum (DRS) and the Capacity Demand Diagram (CDD) that suppose an important change in the way of presenting the Elastic Response Spectrum (ERS). On the other hand in case of action of an earthquake, the dynamic characteristics of a soil have been referred traditionally to the speed of the shear waves that can be generated in a site, together with the characteristics of plasticity and damping of the soil. The Principle of the energy conservation explains why a shear upward propagating seismic wave can be amplified when travelling from a medium with high shear wave velocity (rock) to other medium with lower velocity (soil deposit), as it happened in the earthquake of Mexico of 1985. This amplification is a function of the speed gradient or of the contrast of impedances in the border of both types of mediums. A method is proposed in this paper for the design of containment walls in different soils, suffering to the action of an earthquake, based on the Performance-Based Seismic Design.

Lateral Dynamic Models for High-Speed Railway Bridges and Vehicles

The analysis of the running safety of railway vehicles on viaducts subject to strong lateral actions such as cross winds requires coupled nonlinear vehicle-bridge interaction models, capable to study extreme events. In this paper original models developed by the authors are described, based on finite elements for the structure, multibody and finite element models for the vehicle, and specially developed interaction elements for the interface between wheel and rail. The models have been implemented within ABAQUS and have full nonlinear capabilities for the structure, the vehicle and the contact interface. An application is developed for the Ulla Viaduct, a 105 m tall arch in the Spanish high-speed railway network. The dynamic analyses allow obtaining critical wind curves, which define the running safety conditions for a given train in terms of speed of circulation and wind speed

Usability study for the design of a communicator for ICU patients with communication difficulties

Most of the patients that reside in the intensive care unit experience fear, frustration and high levels of anxiety as they are not able to communicate properly. In this sense, the use of communication tools can be helpful to reduce the frustration levels and also, to improve the efficiency and the speed of the communication. The objective of this work, is to design a tool that allows solving the communication problems that patients suffer when they are admitted in the intensive care unit. In order to achieve the objective of this work, a qualitative study that involved interviews with former patients, hospital staff members and family relatives was performed. Afterwards, the design of a prototype was developed to later conduct and analyze usability evaluations with former patients, hospital staff members and patients relatives. The results expose that participants of the usability evaluations were able to perform most of the tasks effectively.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Dissociation of HIV-1 from follicular dendritic cells during HAART: Mathematical analysis

Follicular dendritic cells (FDC) provide a reservoir for HIV type 1 (HIV-1) that may reignite infection if highly active antiretroviral therapy (HAART) is withdrawn before virus on FDC is cleared. To estimate the treatment time required to eliminate HIV-1 on FDC, we develop deterministic and stochastic models for the reversible binding of HIV-1 to FDC via ligand–receptor interactions and examine the consequences of reducing the virus available for binding to FDC. Analysis of these models shows that the rate at which HIV-1 dissociates from FDC during HAART is biphasic, with an initial period of rapid decay followed by a period of slower exponential decay. The speed of the slower second stage of dissociation and the treatment time required to eradicate the FDC reservoir of HIV-1 are insensitive to the number of virions bound and their degree of attachment to FDC before treatment. In contrast, the expected time required for dissociation of an individual virion from FDC varies sensitively with the number of ligands attached to the virion that are available to interact with receptors on FDC. Although most virions may dissociate from FDC on the time scale of days to weeks, virions coupled to a higher-than-average number of ligands may persist on FDC for years. This result suggests that HAART may not be able to clear all HIV-1 trapped on FDC and that, even if clearance is possible, years of treatment will be required.

Absence of a barrier to backwards rotation of the bacterial flagellar motor demonstrated with optical tweezers

A cell of the bacterium Escherichia coli was tethered covalently to a glass coverslip by a single flagellum, and its rotation was stopped by using optical tweezers. The tweezers acted directly on the cell body or indirectly, via a trapped polystyrene bead. The torque generated by the flagellar motor was determined by measuring the displacement of the laser beam on a quadrant photodiode. The coverslip was mounted on a computer-controlled piezo-electric stage that moved the tether point in a circle around the center of the trap so that the speed of rotation of the motor could be varied. The motor generated ≈4500 pN nm of torque at all angles, regardless of whether it was stalled, allowed to rotate very slowly forwards, or driven very slowly backwards. This argues against models of motor function in which rotation is tightly coupled to proton transit and back-transport of protons is severely limited.

Microtubule-dependent Recruitment of Staufen-Green Fluorescent Protein into Large RNA-containing Granules and Subsequent Dendritic Transport in Living Hippocampal NeuronsV⃞

Dendritic mRNA transport and local translation at individual potentiated synapses may represent an elegant way to form synaptic memory. Recently, we characterized Staufen, a double-stranded RNA-binding protein, in rat hippocampal neurons and showed its presence in large RNA-containing granules, which colocalize with microtubules in dendrites. In this paper, we transiently transfect hippocampal neurons with human Staufen-green fluorescent protein (GFP) and find fluorescent granules in the somatodendritic domain of these cells. Human Stau-GFP granules show the same cellular distribution and size and also contain RNA, as already shown for the endogenous Stau particles. In time-lapse videomicroscopy, we show the bidirectional movement of these Staufen-GFP–labeled granules from the cell body into dendrites and vice versa. The average speed of these particles was 6.4 μm/min with a maximum velocity of 24.3 μm/min. Moreover, we demonstrate that the observed assembly into granules and their subsequent dendritic movement is microtubule dependent. Taken together, we have characterized a novel, nonvesicular, microtubule-dependent transport pathway involving RNA-containing granules with Staufen as a core component. This is the first demonstration in living neurons of movement of an essential protein constituent of the mRNA transport machinery.

The Dynamic Behavior of Individual Microtubules Associated with Chromosomes In Vitro

Mitotic movements of chromosomes are usually coupled to the elongation and shortening of the microtubules to which they are bound. The lengths of kinetochore-associated microtubules change by incorporation or loss of tubulin subunits, principally at their chromosome-bound ends. We have reproduced aspects of this phenomenon in vitro, using a real-time assay that displays directly the movements of individual chromosome-associated microtubules as they elongate and shorten. Chromosomes isolated from cultured Chinese hamster ovary cells were adhered to coverslips and then allowed to bind labeled microtubules. In the presence of tubulin and GTP, these microtubules could grow at their chromosome-bound ends, causing the labeled segments to move away from the chromosomes, even in the absence of ATP. Sometimes a microtubule would switch to shortening, causing the direction of movement to change abruptly. The link between a microtubule and a chromosome was mechanically strong; 15 pN of tension was generally insufficient to detach a microtubule, even though it could add subunits at the kinetochore–microtubule junction. The behavior of the microtubules in vitro was regulated by the chromosomes to which they were bound; the frequency of transitions from polymerization to depolymerization was decreased, and the speed of depolymerization-coupled movement toward chromosomes was only one-fifth the rate of shortening for microtubules free in solution. Our results are consistent with a model in which each microtubule interacts with an increasing number of chromosome-associated binding sites as it approaches the kinetochore.

Muramic lactam in peptidoglycan of Bacillus subtilis spores is required for spore outgrowth but not for spore dehydration or heat resistance

Bacterial endospores derive much of their longevity and resistance properties from the relative dehydration of their protoplasts. The spore cortex, a peptidoglycan structure surrounding the protoplasm, maintains, and is postulated to have a role in attaining, protoplast dehydration. A structural modification unique to the spore cortex is the removal of all or part of the peptide side chains from the majority of the muramic acid residues and the conversion of 50% of the muramic acid to muramic lactam. A mutation in the cwlD gene of Bacillus subtilis, predicted to encode a muramoyl-l-alanine amidase, results in the production of spores containing no muramic lactam. These spores have normally dehydrated protoplasts but are unable to complete the germination/outgrowth process to produce viable cells. Addition of germinants resulted in the triggering of germination with loss of spore refractility and the release of dipicolinic acid but no degradation of cortex peptidoglycan. Germination in the presence of lysozyme allowed the cwlD spores to produce viable cells and showed that they have normal heat resistance properties. These results (i) suggest that a mechanical activity of the cortex peptidoglycan is not required for the generation of protoplast dehydration but rather that it simply serves as a static structure to maintain dehydration, (ii) demonstrate that degradation of cortex peptidoglycan is not required for spore solute release or partial spore core rehydration during germination, (iii) indicate that muramic lactam is a major specificity determinant of germination lytic enzymes, and (iv) suggest the mechanism by which the spore cortex is degraded during germination while the germ cell wall is left intact.

Fluctuations and stimulus-induced changes in blood flow observed in individual capillaries in layers 2 through 4 of rat neocortex

Cortical blood flow at the level of individual capillaries and the coupling of neuronal activity to flow in capillaries are fundamental aspects of homeostasis in the normal and the diseased brain. To probe the dynamics of blood flow at this level, we used two-photon laser scanning microscopy to image the motion of red blood cells (RBCs) in individual capillaries that lie as far as 600 μm below the pia mater of primary somatosensory cortex in rat; this depth encompassed the cortical layers with the highest density of neurons and capillaries. We observed that the flow was quite variable and exhibited temporal fluctuations around 0.1 Hz, as well as prolonged stalls and occasional reversals of direction. On average, the speed and flux (cells per unit time) of RBCs covaried linearly at low values of flux, with a linear density of ≈70 cells per mm, followed by a tendency for the speed to plateau at high values of flux. Thus, both the average velocity and density of RBCs are greater at high values of flux than at low values. Time-locked changes in flow, localized to the appropriate anatomical region of somatosensory cortex, were observed in response to stimulation of either multiple vibrissae or the hindlimb. Although we were able to detect stimulus-induced changes in the flux and speed of RBCs in some single trials, the amplitude of the stimulus-evoked changes in flow were largely masked by basal fluctuations. On average, the flux and the speed of RBCs increased transiently on stimulation, although the linear density of RBCs decreased slightly. These findings are consistent with a stimulus-induced decrease in capillary resistance to flow.

Mannose Inhibits Arabidopsis Germination via a Hexokinase-Mediated Step1

Low concentrations of the glucose (Glc) analog mannose (Man) inhibit germination of Arabidopsis seeds. Man is phosphorylated by hexokinase (HXK), but the absence of germination was not due to ATP or phosphate depletion. The addition of metabolizable sugars reversed the Man-mediated inhibition of germination. Carbohydrate-mediated regulation of gene expression involving a HXK-mediated pathway is known to be activated by Glc, Man, and other monosaccharides. Therefore, we investigated whether Man blocks germination through this system. By testing other Glc analogs, we found that 2-deoxyglucose, which, like Man, is phosphorylated by HXK, also blocked germination; no inhibition was observed with 6-deoxyglucose or 3-O-methylglucose, which are not substrates for HXK. Since these latter two sugars are taken up at a rate similar to that of Man, uptake is unlikely to be involved in the inhibition of germination. Furthermore, we show that mannoheptulose, a specific HXK inhibitor, restores germination of seeds grown in the presence of Man. We conclude that HXK is involved in the Man-mediated repression of germination of Arabidopsis seeds, possibly via energy depletion.

An approach to three-dimensional structures of biomolecules by using single-molecule diffraction images

We describe an approach to the high-resolution three-dimensional structural determination of macromolecules that utilizes ultrashort, intense x-ray pulses to record diffraction data in combination with direct phase retrieval by the oversampling technique. It is shown that a simulated molecular diffraction pattern at 2.5-Å resolution accumulated from multiple copies of single rubisco biomolecules, each generated by a femtosecond-level x-ray free electron laser pulse, can be successfully phased and transformed into an accurate electron density map comparable to that obtained by more conventional methods. The phase problem is solved by using an iterative algorithm with a random phase set as an initial input. The convergence speed of the algorithm is reasonably fast, typically around a few hundred iterations. This approach and phasing method do not require any ab initio information about the molecule, do not require an extended ordered lattice array, and can tolerate high noise and some missing intensity data at the center of the diffraction pattern. With the prospects of the x-ray free electron lasers, this approach could provide a major new opportunity for the high-resolution three-dimensional structure determination of single biomolecules.