Clinical implementation of dynamic multileaf collimation for compensated bladder treatments.

BACKGROUND AND PURPOSE: To describe the clinical implementation of dynamic multileaf collimation (DMLC). Custom compensated four-field treatments of carcinoma of the bladder have been used as a simple test site for the introduction of intensity modulated radiotherapy.MATERIALS AND METHODS: Compensating intensity modulations are calculated from computed tomography (CT) data, accounting for scattered, as well as primary radiation. Modulations are converted to multileaf collimator (MLC) leaf and jaw settings for dynamic delivery on a linear accelerator. A full dose calculation is carried out, accounting for dynamic leaf and jaw motion and transmission through these components. Before treatment, a test run of the delivery is performed and an absolute dose measurement made in a water or solid water phantom. Treatments are verified by in vivo diode measurements and real-time electronic portal imaging. RESULTS: Seven patients have been treated using DMLC. The technique improves dose homogeneity within the target volume, reducing high dose areas and compensating for loss of scatter at the beam edge. A typical total treatment time is 20 min. CONCLUSIONS: Compensated bladder treatments have proven an effective test site for DMLC in an extremely busy clinic.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

An Extended Implementation of the Great Deluge Algorithm for Course Timetabling

Course Scheduling consists of assigning lecture events to a limited set of specific timeslots and rooms. The objective is to satisfy as many soft constraints as possible, while maintaining a feasible solution timetable. The most successful techniques to date require a compute-intensive examination of the solution neighbourhood to direct searches to an optimum solution. Although they may require fewer neighbourhood moves than more exhaustive techniques to gain comparable results, they can take considerably longer to achieve success. This paper introduces an extended version of the Great Deluge Algorithm for the Course Timetabling problem which, while avoiding the problem of getting trapped in local optima, uses simple Neighbourhood search heuristics to obtain solutions in a relatively short amount of time. The paper presents results based on a standard set of benchmark datasets, beating over half of the currently published best results with in some cases up to 60% of an improvement.

High Speed FPGA-based implementations of Delayed-LMS filters

A variation of the least means squares (LMS) algorithm, called the delayed LMS (DLMS) algorithm is an ideally suited to achieve highly pipelined, adaptive digital filter implementations. The paper presents an efficient method of determining the delays in the DLMS filter and then transferring these delays using retiming in order to achieve fully pipelined circuit architectures for FPGA implementation. The method has been used to derive a series of retimed delayed LMS (RDLMS) architectures, which considerable reduce the number of delays and convergence time and give superior performance in terms of throughput rate when compared to previous work. Three circuit architectures and three hardware shared versions are presented which have been implemented using the Virtex-II FPGA technology resulting in a throughout rate of 182 Msample/s.