Understanding the building-up process of three dimensional open-framework metal phosphates: Acid degradation of the 3D structures to lower dimensional structures

Acid degradation of 3D zinc phosphates primarily yields a one-dimensional ladder compound, an observation that is significant considering that the latter forms 3D structures on heating in water.

Sustainability through remanufacturing in India: a case study on mobile handsets

Remanufacturing activities in India are still in nascent stages. However, the substantial growth of Indian economy, coupled with serious issues of population and environmental burden demands a radical shift in market strategies and legislations. The scattered and inefficient product recovery methods prevalent in India are unable to cope with increasing environmental and economic burden on the society - remanufacturing seems to be a promising strategy to explore for these. Our study investigated from a user's context the opportunity of establishing remanufacturing as a formal activity, answering the fundamental questions of whether remanufactured products would be accepted by Indian consumers and how these will fit into the Indian market. The study of the Indian mobile phone market eco-system showed how mobile phones currently move through the value chain, and the importance of the grey and used phone markets in this movement. A prescriptive model has been proposed which utilizes the usage patterns of different consumer groups to create a self-sustainable demand-supply system, potentially complementing frameworks such as the Automotive Remanufacturing Decision-Making Framework (RDMF). (C) 2011 Elsevier Ltd. All rights reserved.

Enantioselective Formal Synthesis of Palmerolide A

Enantioselective formal synthesis of macrolactone palmerolide A, a polyketide marine natural product, is described. Key strategies in the synthesis include the oxidative furan ring-opening of a chiral furyl carbinol for the installation of the 1,4-dienol core and a Jung nonaldol-aldol reaction for the dienamide core.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

A Coalitional Game Framework for Cooperative Secondary Spectrum Access

We consider a framework in which several service providers offer downlink wireless data access service in a certain area. Each provider serves its end-users through opportunistic secondary spectrum access of licensed spectrum, and needs to pay primary license holders of the spectrum usage based and membership based charges for such secondary spectrum access. In these circumstances, if providers pool their resources and allow end-users to be served by any of the cooperating providers, the total user satisfaction as well as the aggregate revenue earned by providers may increase. We use coalitional game theory to investigate such cooperation among providers, and show that the optimal cooperation schemes can be obtained as solutions of convex optimizations. We next show that under usage based charging scheme, if all providers cooperate, there always exists an operating point that maximizes the aggregate revenue of providers, while presenting each provider a share of the revenue such that no subset of providers has an incentive to leave the coalition. Furthermore, such an operating point can be computed in polynomial time. Finally, we show that when the charging scheme involves membership based charges, the above result holds in important special cases.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Explorations en route to synthesis of tashironins: singlet oxygen cycloaddition to 1,3-cyclopentadienes embedded within allo-cedrane framework

In an approach directed toward a tashironin based complex natural product, efficacy of the singlet oxygen mediated [4+2]-cycloaddition to a tetracyclic cyclopentadiene has been evaluated to install the key cis-1,4-dihydroxy functionality. (C) 2011 Elsevier Ltd. All rights reserved.

GEMS of SAPPhIRE: A Framework for Designing?

This paper proposes a framework of designing for conceptual and early embodiment design that uses physical laws and effects explicitly as a central aspect for designing. This is especially important in domains that make explicit use of physical laws and effects in their design, such as novel sensors. The objectives of the paper are: (a) Develop a model, (b) Empirically evaluate the model and (c) Propose a framework. The model is developed by integrating the activity- and outcome-based elements. The model is validated empirically by analyzing protocols of design sessions to find instances of activities and outcomes. Based on the findings, a framework is proposed on how designing should be done. Elements of GEMS (Generate-Evaluate-Modify-Select) and SAPPhIRE (State change-Action-Part-Phenomenon-Input-oRgan-Effect) are used for developing the model.Empirical evaluation confirms that designing can be modeled with the activity and outcome elements. The paper concludes with the identification of areas that require support and future work.