A proposal for low cross-talk square-lattice photonic crystal waveguide intersection utilizing the symmetry of waveguide modes

We propose an approach to construct waveguide intersections with broad bandwidth and low cross-talk for square-lattice photonic crystals. by utilizing a vanishing overlap of the propagation modes in the waveguides created by defects which support dipole-like defect modes. The finite-difference time-domain method is used to simulate the waveguide intersection created in the two-dimensional square-lattice photonic crystals. Over a bandwidth of 30 nm with the center wavelength at 1300 nm, transmission efficiency above 90% is obtained with cross-talk below -30 dB. Especially, we demonstrate the transmission of a 500-fs pulse at 1.3 Am through the intersection, and the pulse after transmission shows very little distortion while the cross-talk remains at low level meantime. (c) 2006 Elsevier B.V. All rights reserved.

Novel hybrid voltage controlled ring oscillators using single electron and MOS transistors

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.

Characterization of parasitics in TO-packaged high-speed laser modules

An elaborate analysis of the parasitic network of high-speed through-hole packaging (TO)-type laser modules is presented using a small-signal equivalent circuit model. The intrinsic laser diode is obtained using the optical modulation technique, and is embedded into the model as a separate component. Three step-by-step measurements are made for determining the packaging parasitic network, including the test fixture, TO header, submount, bonding wire, and parasitics of the laser chip. A good agreement between simulated and measured results confirms the validation and accuracy of the characterization procedures. Furthermore, several key parasitic elements are found based on the simulation of the high-frequency responses of the packaged devices. It is expected that the 3-dB bandwidth of 12 GHz or more of the low-cost TO packaged laser module may be achieved using the proposed optimization method.

Micro-mould method for self-assembling three-dimensional opal photonic crystals

By vertical sedimentation, silica micro-spheres were grown in different shapes of concave micro-zones which were etched on a (100) p-silicon substrate. The following were found: this method can effectively raise the quality of films by avoiding cracks; the geometry of the micro-zones affects the sediment of the film; regular hexagons and triangles best facilitate the growth of photonic crystals. This method is practical for its ability to fabricate self-assembly photonic crystals in previously designed small areas.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Space grown semi-insulating gallium arsenide single crystal and its application

Low noise field effect transistors and analogue switch integrated circuits (ICs) have been fabricated in semi-insulating gallium arsenide (SI-GaAs) wafers grown in space by direct ion-implantation. The electrical behaviors of the devices and the ICs have surpassed those fabricated in the terrestrially grown SI-GaAs wafers. The highest gain and the lowest noise of the transistors made from space-grown SI-GaAs wafers are 22.8 dB and 0.78 dB, respectively. The threshold back-gating voltage of the ICs made from space-grown SI-GaAs wafers is better than 8.5 V The con-elation between the characterizations of materials and devices is studied systematically. (C) 2002 COSPAR. Published by Elsevier Science Ltd. All rights reserved.

Quantum fluctuation of dissipative mesoscopic capacitance coupling circuit

The quantum wave function and the corresponding energy levels of the dissipative mesoscopic capacitance coupling circuits are obtained by using unitary and linear transformations. The quantum fluctuation of charge and current in an arbitrary eigenstate of the system have been also given. The results show that the fluctuation of charge and current depends on not only the eigenstate but also the electronic device parameters.

Comparison of field effect transistor characteristics between space-grown and earth-grown gallium arsenide single crystal substrates

Semi-insulating gallium arsenide single crystal grown in space has been used in fabricating low noise field effect transistors and analog switch integrated circuits by the direct ion-implantation technique. All key electrical properties of these transistors and integrated circuits have surpassed those made from conventional earth-grown gallium arsenide. This result shows that device-grade space-grown semiconducting single crystal has surpassed the best terrestrial counterparts. (C) 2001 American Institute of Physics.

Defects and morphologies in In0.8Ga0.2As/InAlAs/InP(001) for high electron-mobility transistors

Defects and morphologies are presented in this paper as revealed with transmission electron microscope (TEM) in the In(0.8)G(0.2)As/InAlAs heterostructure on InP(001) for high-electron-mobility transistors application. Most of the misfit dislocation lines are 60 degrees type and they deviate < 110 > at some angles to either side according to their Burges vectors. The misfit dislocation lines deviating [-110] are divided into two types according to whether their edge component b(eg) of Burges vectors in [001] pointing up or down. If b(eg) points up in the growth direction, there is the local periodical strain modulation along the dislocation line. In addition, the periodical modulation in height along [-110] on the In(0.8)G(0.2)As surface is observed, this surface morphology is not associated with the relaxation of mismatch strain.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

Outer space grown semi-insulating GaAs and its applications

GaAs single crystal has been grown in recoverable satellite. Hall measurements indicate that the GaAs shows semi-insulating behavior. The structural properties of the crystal have been improved obviously, and their uniformity has been improved as well. The stoichiometry and its distribution in space-grown GaAs are improved greatly compared with the GaAs single crystal grown terrestrially. The properties of integrated circuits made by direct ion-implantation on space-grown GaAs are better than those made on ground-grown materials. These results show that the stoichiometry in semi-insulating GaAs seriously affects the properties of related devices.

Performing Fast Addition and Multiplication by Transferring Single Electrons

This paper proposes novel fast addition and multiplication circuits that are based on non-binary redundant number systems and single electron (SE) devices. The circuits consist of MOSFET-based single-electron (SE) turnstiles. We use the number of electrons to represent discrete multiple-valued logic states and we finish arithmetic operations by controlling the number of electrons transferred. We construct a compact PD2,3 adder and a 12x12bit multiplier using the PD2,3 adder. The speed of the adder can be as high as 600MHz with 400nW power dissipation. The speed of the adder is regardless of its operand length. The proposed circuits have much smaller transistors than conventional circuits.

Nanoelectronic Circuit Architectures Based on Single-Electron Turnstiles

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile [1] as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator [2] and the single-electron multiple-valued memories (SEMVs) [3]. The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

The design and verification of FPGA CAD toolset

This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.