Methodologies for Synthesizable Programmable Devices based on Multi-Stage Switching Networks

Nowadays the rise of non-recurring engineering (NRE) costs associated with complexity is becoming a major factor in SoC design, limiting both scaling opportunities and the flexibility advantages offered by the integration of complex computational units. The introduction of embedded programmable elements can represent an appealing solution, able both to guarantee the desired flexibility and upgradabilty and to widen the SoC market. In particular embedded FPGA (eFPGA) cores can provide bit-level optimization for those applications which benefits from synthesis, paying on the other side in terms of performance penalties and area overhead with respect to standard cell ASIC implementations. In this scenario this thesis proposes a design methodology for a synthesizable programmable device designed to be embedded in a SoC. A soft-core embedded FPGA (eFPGA) is hence presented and analyzed in terms of the opportunities given by a fully synthesizable approach, following an implementation flow based on Standard-Cell methodology. A key point of the proposed eFPGA template is that it adopts a Multi-Stage Switching Network (MSSN) as the foundation of the programmable interconnects, since it can be efficiently synthesized and optimized through a standard cell based implementation flow, ensuring at the same time an intrinsic congestion-free network topology. The evaluation of the flexibility potentialities of the eFPGA has been performed using different technology libraries (STMicroelectronics CMOS 65nm and BCD9s 0.11μm) through a design space exploration in terms of area-speed-leakage tradeoffs, enabled by the full synthesizability of the template. Since the most relevant disadvantage of the adopted soft approach, compared to a hardcore, is represented by a performance overhead increase, the eFPGA analysis has been made targeting small area budgets. The generation of the configuration bitstream has been obtained thanks to the implementation of a custom CAD flow environment, and has allowed functional verification and performance evaluation through an application-aware analysis.

Simulated switching of the resting state functional connectivity in mouse brain using a real mesoscale connectome

Capire come modellare l'attività del cervello a riposo, resting state, è il primo passo necessario per avvicinarsi a una reale comprensione della dinamica cerebrale. Sperimentalmente si osserva che, quando il cervello non è soggetto a stimoli esterni, particolari reti di regioni cerebrali presentano un'attività neuronale superiore alla media. Nonostante gli sforzi dei ricercatori, non è ancora chiara la relazione che sussiste tra le connessioni strutturali e le connessioni funzionali del sistema cerebrale a riposo, organizzate nella matrice di connettività funzionale. Recenti studi sperimentali mostrano la natura non stazionaria della connettività funzionale in disaccordo con i modelli in letteratura. Il modello implementato nella presente tesi per simulare l'evoluzione temporale del network permette di riprodurre il comportamento dinamico della connettività funzionale. Per la prima volta in questa tesi, secondo i lavori a noi noti, un modello di resting state è implementato nel cervello di un topo. Poco è noto, infatti, riguardo all'architettura funzionale su larga scala del cervello dei topi, nonostante il largo utilizzo di tale sistema nella modellizzazione dei disturbi neurologici. Le connessioni strutturali utilizzate per definire la topologia della rete neurale sono quelle ottenute dall'Allen Institute for Brain Science. Tale strumento fornisce una straordinaria opportunità per riprodurre simulazioni realistiche, poiché, come affermato nell'articolo che presenta tale lavoro, questo connettoma è il più esauriente disponibile, ad oggi, in ogni specie vertebrata. I parametri liberi del modello sono stati scelti in modo da inizializzare il sistema nel range dinamico ottimale per riprodurre il comportamento dinamico della connettività funzionale. Diverse considerazioni e misure sono state effettuate sul segnale BOLD simulato per meglio comprenderne la natura. L'accordo soddisfacente fra i centri funzionali calcolati nel network cerebrale simulato e quelli ottenuti tramite l'indagine sperimentale di Mechling et al., 2014 comprovano la bontà del modello e dei metodi utilizzati per analizzare il segnale simulato.

Studio di un trasformatore trifase ad alta frequenza per convertitori switching

Studio di un trasformatore trifase ad alta frequenza per convertitori switching con prove a vuoto e cortocircuito tramite simulazione software.

Nanoscale switching characteristics of nearly tetragonal BiFeO3 thin films

We have investigated the nanoscale switching properties of strain-engineered BiFeO(3) thin films deposited on LaAlO(3) substrates using a combination of scanning probe techniques. Polarized Raman spectral analysis indicates that the nearly tetragonal films have monoclinic (Cc) rather than P4mm tetragonal symmetry. Through local switching-spectroscopy measurements and piezoresponse force microscopy, we provide clear evidence of ferroelectric switching of the tetragonal phase, but the polarization direction, and therefore its switching, deviates strongly from the expected (001) tetragonal axis. We also demonstrate a large and reversible, electrically driven structural phase transition from the tetragonal to the rhombohedral polymorph in this material, which is promising for a plethora of applications.

Effect of platform switching on peri-implant bone levels: a randomized clinical trial

The concept of platform switching has been introduced to implant dentistry based on observations of reduced peri-implant bone loss. However, randomized clinical trials are still lacking. This study aimed to test the hypothesis that platform switching has a positive impact on crestal bone-level changes.

Open or submerged healing of implants with platform switching: a randomized, controlled clinical trial

The temporal pattern of bone-level alterations in conventionally restored implants is dependent upon healing mode (open or submerged). This study examined the influence of healing on marginal bone levels at implants with a medium-rough surface including the implant collar and a clearance-fit implant-abutment connection restored according to a platform-switching concept.

The causal effect of switching to second-line ART in programmes without access to routine viral load monitoring

We examined the effect of switching to second-line antiretroviral therapy (ART) on mortality in patients who experienced immunological failure in ART programmes without access to routine viral load monitoring in sub-Saharan Africa.

Redox-Switching in a Viologen-type Adlayer: An Electrochemical Shell-Isolated Nanoparticle Enhanced Raman Spectroscopy Study on Au(111)-(1 x 1) Single Crystal Electrodes

We reported the first application of in situ shell-isolated nanoparticle enhanced Raman spectroscopy (SHINERS) to an interfacial redox reaction under electrochemical conditions. We construct gap-mode sandwich structures composed of a thiol-terminated HS-6V6H viologen adlayer immobilized on a single crystal Au(111)-(1x1) electrode and covered by Au(60 nm)@SlO(2) core shell nanoparticles acting as plasmonic antennas. We observed high-quality, potential-dependent Raman spectra of the three viologen species V(2+),V(+center dot) and V(0) on a well-defined Au(111) substrate surface and could map their potential-dependent evolution. Comparison with experiments on powder samples revealed an enhancement factor of the nonresonant Raman modes of similar to 3 x 10(5), and up to 9 x 10(7) for the resonance modes. The study illustrates the unique capability of SHINERS and its potential in the entire field of electrochemical surface science to explore structures and reaction pathways on well-defined substrate surfaces, such as single crystals, for molecular, (electro-)- catalytic, bioelectrochemical systems up to fundamental double layer studies at electrified solid/liquid interfaces.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.