966 resultados para Power circuit
Resumo:
Standard-cell design methodology is an important technique in semicustom-VLSI design. It lends itself to the easy automation of the crucial layout part, and many algorithms have been proposed in recent literature for the efficient placement of standard cells. While many studies have identified the Kerninghan-Lin bipartitioning method as being superior to most others, it must be admitted that the behaviour of the method is erratic, and that it is strongly dependent on the initial partition. This paper proposes a novel algorithm for overcoming some of the deficiencies of the Kernighan-Lin method. The approach is based on an analogy of the placement problem with neural networks, and, by the use of some of the organizing principles of these nets, an attempt is made to improve the behavior of the bipartitioning scheme. The results have been encouraging, and the approach seems to be promising for other NP-complete problems in circuit layout.
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This paper is concerned with the influence of different levels of complexity in modelling various constituent subsystems on the dynamic stability of power systems compensated by static var systems (SVS) operating on pure voltage control. The system components investigated include thyristor controlled reactor (TCR) transients, SVS delays, network transients, the synchronous generator and automatic voltage regulator (AVR). An overall model is proposed which adequately describes the system performance for small signal perturbations. The SVS performance is validated through detailed nonlinear simulation on a physical simulator.
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We present a simple proof of Toda′s result (Toda (1989), in "Proceedings, 30th Annual IEEE Symposium on Foundations of Computer Science," pp. 514-519), which states that circled plus P is hard for the Polynomial Hierarchy under randomized reductions. Our approach is circuit-based in the sense that we start with uniform circuit definitions of the Polynomial Hierarchy and apply the Valiant-Vazirani lemma on these circuits (Valiant and Vazirani (1986), Thoeret. Comput. Sci.47, 85-93).
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Torsional interactions can occur due to the speed input Power System Stabilizer (PSS) that are primarily used to damp low frequency oscillations. The solution to this problem can be either in the form of providing a torsional filter or developing an alternate signal for the PSS. This paper deals with the formulation of a linearized state space model of the system and study of the interactions using eigenvalue analysis. The effects of the parameters of PSS and control signals on the damping of torsional modes are investigated.
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This study aims at understanding the need for decentralized power generation systems and to explore the potential, feasibility and environmental implications of biomass gasifier-based electricity generation systems for village electrification. Electricity needs of villages are in the range of 5–20 kW depending on the size of the village. Decentralized power generation systems are desirable for low load village situations as the cost of power transmission lines is reduced and transmission and distribution losses are minimised. A biomass gasifier-based electricity generation system is one of the feasible options; the technology is readily available and has already been field tested. To meet the lighting and stationary power needs of 500,000 villages in India the land required is only 16 Mha compared to over 100 Mha of degraded land available for tree planting. In fact all the 95 Mt of woody biomass required for gasification could be obtained through biomass conservation programmes such as biogas and improved cook stoves. Thus dedication of land for energy plantations may not be required. A shift to a biomass gasifier-based power generation system leads to local benefits such as village self reliance, local employment and skill generation and promotion of in situ plant diversity plus global benefits like no net CO2 emission (as sustainable biomass harvests are possible) and a reduction in CO2 emissions (when used to substitute thermal power and diesel in irrigation pump sets).
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This paper presents a physical explanation of the phenomenon of low frequency oscillations experienced in power systems. A brief account of the present practice of providing fixed gain power system stabilizers (PSS) is followed by a summary of some of the recent design proposals for adaptive PSS. A novel PSS based on the effort of cancelling the negative damping torque produced by the automatic voltage regulator (AVR) is presented along with some recent studies on a multimachine system using a frequency identification technique.
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Former President of Finland Urho Kekkonen was not only a powerful politician but also a well-known sportsman and keep-fit enthusiast. The president’s sports hobbies were covered and celebrated in the media and thus became an integral part of his public persona. This paper looks at Kekkonen’s athletic and able-bodied image and its significance for his power from the perspective of gender. In his exercise activities, Kekkonen was able to display his bodily prowess and demonstrate his version of masculinity, which emphasized both physical and mental strength. The union of mind and muscle in turn buttressed his political ascendancy. Kekkonen’s athletic body served as a cornerstone of his dominance over his country and, simultaneously, as a shield protecting Finland from both internal and external threats. Furthermore, Kekkonen’s sports performances were essential elements in the myth that was created around the president during his term and which was carefully conserved after his fall from power. Drawing upon scholarship on men and masculinities, this paper reassesses the still-effective mythical image of Kekkonen as an invincible superman. The article reveals the performative nature of his athletic activities and shows that in part, his pre-eminence in them was nothing more than theatre enacted by him and his entourage. Thus, Kekkonen’s superior and super-masculine image was actually surprisingly vulnerable and dependent on the success of the performance. The president’s ageing, in particular, demonstrates the fragility of his displays of prowess, strength and masculinity, and shows how fragile the entanglement of body and power can be.
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Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.
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A simple yet accurate equivalent circuit model was developed for the analysis of slow-wave properties (dispersion and interaction impedance characteristics) of a rectangular folded-waveguide slow-wave structure. Present formulation includes the effects of the presence of beam-hole in the circuit, which were ignored in existing approaches. The analysis was benchmarked against measurement as well as with 3D electromagnetic modeling using MAFIA for two typical slow-wave structures operating in Ka- and Q-bands, and close agreements were observed. The analysis was extended for demonstrating the effect of the variation of beam-hole radius on the RF interaction efficiency of the device. (C) 2009 Elsevier GmbH. All rights reserved.
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This paper presents the analysis and study of voltage collapse at any converter bus in an AC system interconnected by multiterminal DC (MTDC) links. The analysis is based on the use of the voltage sensitivity factor (VSF) as a voltage collapse proximity indicator (VCPI). In this paper the VSF is defined as a matrix which is applicable to MTDC systems. The VSF matrix is derived from the basic steady state equations of the converter, control, DC and AC networks. The structure of the matrix enables the derivation of some of the basic properties which are generally applicable. A detailed case study of a four-terminal MTDC system is presented to illustrate the effects of control strategies at the voltage setting terminal (VST) and other terminals. The controls considered are either constant angle, DC voltage, AC voltage, reactive current and reactive power at the VST and constant power or current at the other terminals. The effect of the strength of the AC system (measured by short circuit ratio) on the VSF is investigated. Several interesting and new results are presented. An analytical expression for the self VSF at VST is also derived for some specific cases which help to explain the number of transitions in VSF around the critical values of SCR.
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Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file. We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine. (C) 2010 Elsevier B.V. All rights reserved.
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Large external memory bandwidth requirement leads to increased system power dissipation and cost in video coding application. Majority of the external memory traffic in video encoder is due to reference data accesses. We describe a lossy reference frame compression technique that can be used in video coding with minimal impact on quality while significantly reducing power and bandwidth requirement. The low cost transformless compression technique uses lossy reference for motion estimation to reduce memory traffic, and lossless reference for motion compensation (MC) to avoid drift. Thus, it is compatible with all existing video standards. We calculate the quantization error bound and show that by storing quantization error separately, bandwidth overhead due to MC can be reduced significantly. The technique meets key requirements specific to the video encode application. 24-39% reduction in peak bandwidth and 23-31% reduction in total average power consumption are observed for IBBP sequences.
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Design, fabrication and preliminary testing of a flat pump with millimetre thickness are described in this paper. The pump is entirely made of polymer materials barring the magnet and copper coils used for electromagnetic actuation. The fabrication is carried out using widely available microelectronic packaging machinery and techniques. Therefore, the fabrication of the pump is straightforward and inexpensive. Two types of prototypes are designed and built. One consists of copper coils that are etched on an epoxy plate and the other has wound insulated wire of 90 mu m diameter to serve as a coil. The overall size of the first pump is 25 mm x 25 mm x 3.6 mm including the 3.1 mm-thick NdFeB magnet of diameter 12 mm. It consists of a pump chamber of 20 mm x 20 mm x 0.8 mm with copper coils etched from a copper-clad epoxy plate using dry-film lithography and milled using a CNC milling machine, two passive valves and the pump-diaphragm made of Kapton film of 0.089 mm thickness. The second pump has an overall size of 35 mm x 35 mm x 4.4 mm including the magnet and the windings. A breadboard circuit and DC power supply are used to test the pump by applying an alternating square-wave voltage pulse. A water slug in a tube attached to the inlet is used to observe and measure the air-flow induced by the pump against atmospheric pressure. The maximum flow rate was found to be 15 ml/min for a voltage of 2.5 V and a current of 19 mA at 68 Hz.
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Downward seepage (suction) increases the mobility of the channel. In this study, experimental investigations were carried out to analyse the suction effect on stream power along the downstream side of the flume. It was observed that stream power has a major influence on the stability and mobility of the bed particles, due to suction. Stream power is found to be greater at the upstream side and lower at the downstream side. This reduces the increment in the mobility of the sand particles due to suction at the downstream side. Thus, there is more erosion at the upstream side than the downstream side. It was also found that the amount of deposition of sand particles at the downstream side, because of the high stream power at the upstream side, is greater than the amount of erosion of sand particles from the downstream side.
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Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random ``care'' bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.