Tellurium enhanced non-resonant third-order optical nonlinearity in a germano-silicate optical fiber

碲掺杂的高非线性石英光纤

ENHANCEMENT EFFECT OF PLASMA-ENHANCED CHEMICAL-VAPOR-DEPOSITED SIN CAPPING LAYER ON DIELECTRIC CAP QUANTUM-WELL DISORDERING

Quantum well disordering of GaAs/AlGaAs multiple quantum well(MQW) has been accomplished with only plasma enhanced chemical vapor deposited (PECVD) SiN cap layer growth. The amount of blue shift increases with SiN growing time. This result has been explained by the vacancy indiffusion during PECVD SiN growth. Rapid thermal annealing (RTA) of the sample after SiN cap layer growth at 850 degrees C for 35 s caused a larger amount of blue shift than those obtained without RTA. By considering the model of Al diffusion from AlGaAs barrier into GaAs QWs together with the result from photoluminescence (PL) measurement, Al diffusion coefficients were calculated. The Al diffusion coefficient due to PECVD SiN was estimated at about 3 x10(-17) cm(2)/s. It was possible to extract the effect of RTA on the QW disordering, which showed that the amount of the blue shift and the Al diffusion coefficient due only to RTA increases with SiN cap layer thickness as reported by Chi et al.(10))

Ag surface plasmon enhanced double-layer antireflection coatings for GaAs solar cells

Surface plasmon enhanced antireflection coatings for GaAs solar cells have been designed theoretically. The reflectance of double-layer antireflection coatings (ARCs) with different suspensions of Ag particles is calculated as a function of the wavelength according to the optical interference matrix and the Mie theory. The mean dielectric concept was adopted in the simulations. A significant reduction of reflectance in the spectral region from 300 to 400 nm was found to be beneficial for the design of ARCs. A new SiO_2/Ag-ZnS double-layer coating with better antireflection ability can be achieved if the particle volume fraction in ZnS is 1%-2%.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.