Using Level Sets as the basis for a scalable, parallel geometry engine and mesh generation system

The background to this review paper is research we have performed over recent years aimed at developing a simulation system capable of handling large scale, real world applications implemented in an end-to-end parallel, scalable manner. The particular focus of this paper is the use of a Level Set solid modeling geometry kernel within this parallel framework to enable automated design optimization without topological restrictions and on geometries of arbitrary complexity. Also described is another interesting application of Level Sets: their use in guiding the export of a body-conformal mesh from our basic cut-Cartesian background octree - mesh - this permits third party flow solvers to be deployed. As a practical demonstrations meshes of guaranteed quality are generated and flow-solved for a B747 in full landing configuration and an automated optimization is performed on a cooled turbine tip geometry. Copyright © 2009 by W.N.Dawes.

Improved infrared thermal imaging of a CMOS MEMS device

We report a technique which can be used to improve the accuracy of infrared (IR) surface temperature measurements made on MEMS (Micro-Electro-Mechanical- Systems) devices. The technique was used to thermally characterize a SOI (Silicon-On-Insulator) CMOS (Complementary Metal Oxide Semiconductor) MEMS thermal flow sensor. Conventional IR temperature measurements made on the sensor were shown to give significant surface temperature errors, due to the optical transparency of the SiO 2 membrane layers and low emissivity/high reflectivity of the metal. By making IR measurements on radiative carbon micro-particles placed in isothermal contact with the device, the accuracy of the surface temperature measurement was significantly improved. © 2010 EDA Publishing/THERMINIC.

Thermal characterization of SOI CMOS micro hot-plate gas sensors

This work reports on thermal characterization of SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) MEMS (micro electro mechanical system) gas sensors using a thermoreflectance (TR) thermography system. The sensors were fabricated in a CMOS foundry and the micro hot-plate structures were created by back-etching the CMOS processed wafers in a MEMS foundry using DRIE (deep reactive ion etch) process. The calibration and experimental details of the thermoreflectance based thermal imaging setup, used for these micro hot-plate gas sensor structures, are presented. Experimentally determined temperature of a micro hot-plate sensor, using TR thermography and built-in silicon resistive temperature sensor, is compared with that estimated using numerical simulations. The results confirm that TR based thermal imaging technique can be used to determine surface temperature of CMOS MEMS devices with a high accuracy. © 2010 EDA Publishing/THERMINIC.

Configural processing of different topologically structured figures: an ERP Study

According to Chen's theory, topological differences are perceived faster than feature differences in early visual perception. We hypothesized that topological perception is caused by the sensitivity in discriminating figures with and without "holes". An E

Different masking effects on "hole" and "no-hole" figures

Global information is considered the primitive of visual perception in Gestalt psychology. Further, L. Chen ( 2005) proposed a new theory of topological visual perception. According to this theory, the perception of topological difference is faster than o

An approach to functional synthesis of solutions in mechanical conceptual design. Part III: Spatial configuration

These three papers describe an approach to the synthesis of solutions to a class of mechanical design problems; these involve transmission and transformation of mechanical forces and motion, and can be described by a set of inputs and outputs. The approach involves (1) identifying a set of primary functional elements and rules of combining them, and (2) developing appropriate representations and reasoning procedures for synthesising solution concepts using these elements and their combination rules; these synthesis procedures can produce an exhaustive set of solution concepts, in terms of their topological as well as spatial configurations, to a given design problem. This paper (Part III) describes a constraint propagation procedure which, using a knowledge base of spatial information about a set of primary functional elements, can produce possible spatial configurations of solution concepts generated in Part II.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Zinc oxide nanowire based hydrogen sensor on SOI CMOS platform

Here we report on the successful low-temperature growth of zinc oxide nanowires (ZnONWs) on silicon-on-insulator (SOI) CMOS micro-hotplates and their response, at different operating temperatures, to hydrogen in air. The SOI micro-hotplates were fabricated in a commercial CMOS foundry followed by a deep reactive ion etch (DRIE) in a MEMS foundry to form ultra-low power membranes. The micro-hotplates comprise p+ silicon micro-heaters and interdigitated metal electrodes (measuring the change in resistance of the gas sensitive nanomaterial). The ZnONWs were grown as a post-CMOS process onto the hotplates using a CMOS friendly hydrothermal method. The ZnONWs showed a good response to 500 to 5000 ppm of hydrogen in air. We believe that the integration of ZnONWs with a MEMS platform results in a low power, low cost, hydrogen sensor that would be suitable for handheld battery-operated gas sensors. © 2011 Published by Elsevier Ltd.

Hot electron field emission via individually transistor-ballasted carbon nanotube arrays.

We present electronically controlled field emission characteristics of arrays of individually ballasted carbon nanotubes synthesized by plasma-enhanced chemical vapor deposition on silicon-on-insulator substrates. By adjusting the source-drain potential we have demonstrated the ability to controllable limit the emission current density by more than 1 order of magnitude. Dynamic control over both the turn-on electric field and field enhancement factor have been noted. A hot electron model is presented. The ballasted nanotubes are populated with hot electrons due to the highly crystalline Si channel and the high local electric field at the nanotube base. This positively shifts the Fermi level and results in a broad energy distribution about this mean, compared to the narrow spread, lower energy thermalized electron population in standard metallic emitters. The proposed vertically aligned carbon nanotube field-emitting electron source offers a viable platform for X-ray emitters and displays applications that require accurate and highly stable control over the emission characteristics.

Electronic and magnetic properties of Ti(2)O(3), Cr(2)O(3), and Fe(2)O(3) calculated by the screened exchange hybrid density functional.

The electronic and magnetic properties of the transition metal sesqui-oxides Cr(2)O(3), Ti(2)O(3), and Fe(2)O(3) have been calculated using the screened exchange (sX) hybrid density functional. This functional is found to give a band structure, bandgap, and magnetic moment in better agreement with experiment than the local density approximation (LDA) or the LDA+U methods. Ti(2)O(3) is found to be a spin-paired insulator with a bandgap of 0.22 eV in the Ti d orbitals. Cr(2)O(3) in its anti-ferromagnetic phase is an intermediate charge transfer Mott-Hubbard insulator with an indirect bandgap of 3.31 eV. Fe(2)O(3), with anti-ferromagnetic order, is found to be a wide bandgap charge transfer semiconductor with a 2.41 eV gap. Interestingly sX outperforms the HSE functional for the bandgaps of these oxides.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

Ballasted & electrically steerable carbon nanotube field emitters

Here we present our on-going efforts toward the development of stable ballasted carbon nanotube-based field emitters employing hydrothermally synthesized zinc oxide nanowires and thin film silicon-on-insulator substrates. The semiconducting channel in each controllably limits the emission current thereby preventing detrimental burn-out of individual emitters that occurs due to unavoidable statistical variability in emitter characteristics, particularly in their length. Fabrication details and emitter characterization are discussed in addition to their field emission performance. The development of a beam steerable triode electron emitter formed from hexagonal carbon nanotube arrays with central focusing nanotube electrodes, is also described. Numerical ab-initio simulations are presented to account for the empirical emission characteristics. Our engineered ballasted emitters have shown some of the lowest reported lifetime variations (< 0.7%) with on-times of < 1 ms, making them ideally-suited for next-generation displays, environmental lighting and portable x-rays sources. © 2012 SPIE.

The lateral superjunction PSOI LIGBT and LDMOSFET

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18μm PSOI HV process. The superjunction drift region helps in achieving uniform electric field distribution in both structures but also contributes to the on-state current in the LIGBT. The superjunction LIGBT successfully achieves breakdown voltage (BV) of 210V with Rdson of 765mΩ.mm2. It exhibits reduced specific on-state resistance Rdson and higher saturation current (Idsat) for the same BV compared to a compatible lateral superjunction LDMOS in the same technology. © 2012 IEEE.

SOI membrane-based pressure sensor in stress sensitive differential amplifier configuration

This paper introduces a pressure sensing structure configured as a stress sensitive differential amplifier (SSDA), built on a Silicon-on-Insulator (SOI) membrane. Theoretical calculation show the significant increase in sensitivity which is expected from the pressure sensors in SSDA configuration compared to the traditional Wheatstone bridge circuit. Preliminary experimental measurements, performed on individual transistors placed on the membrane, exhibit state-the-art sensitivity values (1.45mV/mbar). © 2012 IEEE.

SOI sensing technologies for harsh environment

This paper reviews and addresses certain aspects of Silicon-On-Insulator (SOI) technologies for a harsh environment. The paper first describes the need for specialized sensors in applications such as (i) domestic and other small-scale boilers, (ii) CO2 Capture and Sequestration, (iii) oil & gas storage and transportation, and (iv) automotive. We describe in brief the advantages and special features of SOI technology for sensing applications requiring temperatures in excess of the typical bulk silicon junction temperatures of 150oC. Finally we present the concepts, structures and prototypes of simple and smart micro-hotplate and Infra Red (IR) based emitters for NDIR (Non Dispersive IR) gas sensors in harsh environments. © 2012 IEEE.