921 resultados para self-organized critical
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Electronics Letters Vol.38, nº 19
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We numerically study a simple fluid composed of particles having a hard-core repulsion complemented by two patchy attractive sites on the particle poles. An appropriate choice of the patch angular width allows for the formation of ring structures which, at low temperatures and low densities, compete with the growth of linear aggregates. The simplicity of the model makes it possible to compare simulation results and theoretical predictions based on the Wertheim perturbation theory, specialized to the case in which ring formation is allowed. Such a comparison offers a unique framework for establishing the quality of the analytic predictions. We find that the Wertheim theory describes remarkably well the simulation results.
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We investigate the nature of the ordered phase and the orientational correlations between adjacent layers of the confined three-dimensional self-assembled rigid rod model, on the cubic lattice. We find that the ordered phase at finite temperatures becomes uniaxial in the thermodynamic limit, by contrast to the ground state (partial) order where the orientation of the uncorrelated layers is perpendicular to one of the three lattice directions. The increase of the orientational correlation between layers as the number of layers increases suggests that the unconfined model may also exhibit uniaxial ordering at finite temperatures.
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Dissertação apresentada como requisito parcial para obtenção do grau de Mestre em Estatística e Gestão de Informação
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Relatório da Prática Profissional Supervisionada Mestrado em Educação Pré-Escolar
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Relatório da Prática Profissional Supervisionada Mestrado em Educação Pré-Escolar
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Relatório da Prática Profissional Supervisionada Mestrado em Educação Pré-Escolar
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Educação Médica. 1994, 5(3):178-181.
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To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.
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To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.
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The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly
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Doutoramento em Ciências da Comunicação - Especialidade de Comunicação e Artes
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Dissertação apresentada como requisito parcial para obtenção do grau de Mestre em Ciência e Sistemas de Informação Geográfica
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Dissertação apresentada como requisito parcial para obtenção do grau de Mestre em Ciência e Sistemas de Informação Geográfica
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IEEE International Symposium on Circuits and Systems, pp. 232 – 235, Seattle, EUA