A study of the configurations of boron in silicon using an empirical approach

The configuration space of boron in silicon has been investigated using an empirical potential approach. This study indicates that energetically favourable configurations consist of a number of three-fold coordinated split interstitials. A configuration consisting of a four-fold boron-interstitial in combination with a two-fold silicon is found to be perfectly aligned in the <111> direction. This configuration in the positive charge state is a possibility for the boron interstitial related defect found via EPR and DLTS. © 1994.

Tetrahedral amorphous carbon-silicon heterojunction band energy offsets

Non-hydrogenated tetrahedral amorphous carbon (ta-C) has shown superior field emission characteristics. The understanding of the emission mechanism has been hindered by the lack of any directly measured data on the band offsets between ta-C and Si. In this paper results from direct in situ X-ray photoemission spectroscopy (XPS) measurements of the band-offset between ta-C and Si are reported. The measurements were carried out using a filtered cathodic vacuum arc (FCVA) deposition system attached directly to an ultra-high vacuum (UHV) XPS chamber via a load lock chamber. Repeated XPS measurements were carried out after monolayer depositions on in situ cleaned Si substrates. The total film thickness for each set of measurements was approximately 5 nm. Analysis of the data from undoped ta-C on n and p Si show the unexpected result that the conduction band barrier between Si and ta-C remains around 1.0 eV, but that the valence band barrier changes from 0.7 to 0.0 eV. The band line up derived from these barriers suggests that the Fermi level in the ta-C lies 0.3 eV above the valence band on both p and n+Si. The heterojunction barriers when ta-C is doped with nitrogen are also presented. The implications of the heterojunction energy barrier heights for field emission from ta-C are discussed.

Defined etching of carbon-diamond films on silicon using an oxygen plasma with titanium masking

A technique for pattern transfer onto carbon-diamond films deposited by radio-frequency plasma-enhanced chemical vapour deposition is reported. Such a technique involves standard photolithography processes and reactive ion etching by oxygen and is compatible with present day microelectronic technology. The patterns transferred are well defined with very good resolution. © 1992.

A study of frequency response in silicon heterojunction bipolar transistors with amorphous silicon emitters

A detailed physical model of amorphous silicon (aSi:H) is incorporated into a twodimensional device simulator to examine the frequency response limits of silicon heterojunction bipolar transistors (HBT's) with aSi:H emitters. The cutoff frequency is severely limited by the transit time in the emitter space charge region, due to the low electron drift mobility in aSi:H, to 98 MHz which compares poorly with the 37 GHz obtained for a silicon homojunction bipolar transistor with the same device structure. The effects of the amorphous heteroemitter material parameters (doping, electron drift mobility, defect density and interface state density) on frequency response are then examined to find the requirements for an amorphous heteroemitter material such that the HBT has better frequency response than the equivalent homojunction bipolar transistor. We find that an electron drift mobility of at least 100 cnr'V"'"1 is required in the amorphous heteroemitter and at a heteroemitter drift mobility of 350 cm2 · V1· s1 and heteroemitter doping of 5×1017 cm3, a maximum cutoff frequency of 52 GHz can be expected. © 1996 IEEE.

Computation of high-stability DC balancing scheme for ferroelectric liquid crystal on silicon holograms using graphics processing units.

Spatial light modulators based around liquid crystal on silicon have found use in a variety of telecommunications applications, including the optimization of multimode fibers, free-space communications, and wavelength selective switching. Ferroelectric liquid crystals are attractive in these areas due to their fast switching times and high phase stability, but the necessity for the liquid crystal to spend equal time in each of its two possible states is an issue of practical concern. Using the highly parallel nature of a graphics processing unit architecture, it is possible to calculate DC balancing schemes of exceptional quality and stability.

Liquid crystal over silicon device characteristics for holographic projection of high-definition television images.

We discuss some fundamental characteristics of a phase-modulating device suitable to holographically project a monochrome video frame with 1280 x 720 resolution. The phase-modulating device is expected to be a liquid crystal over silicon chip with silicon area similar to that of commercial devices. Its basic characteristics, such as number of pixels, bits per pixel, and pixel dimensions, are optimized in terms of image quality and optical efficiency. Estimates of the image quality are made from the noise levels and contrast, while efficiency is calculated by considering the beam apodization, device dead space, diffraction losses, and the sinc envelope.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Trapped charge dynamics in a sol-gel based TiO(2) high- k gate dielectric silicon metal-oxide-semiconductor field effect transistor.

We have studied the response of a sol-gel based TiO(2), high k dielectric field effect transistor structure to microwave radiation. Under fixed bias conditions the transistor shows frequency dependent current fluctuations when exposed to continuous wave microwave radiation. Some of these fluctuations take the form of high Q resonances. The time dependent characteristics of these responses were studied by modulating the microwaves with a pulse signal. The measurements show that there is a shift in the centre frequency of these high Q resonances when the pulse time is varied. The measured lifetime of these resonances is high enough to be useful for non-classical information processing.