Effect of Post-Metallization Hydrogen Annealing on C-V Characteristic of Zirconia Grown Using Atomic Layer Deposition

Substantial amount of fixed charge present in most of the alternative gate dielectrics gives rise to large shifts in the flat-band voltage (VFB) and charge trapping and de-trapping causes hysterectic changes on voltage cycling. Both phenomena affect stable and reliable transistor operation. In this paper we have studied for the first time the effect of post-metallization hydrogen annealing on the C-V curve of MOS capacitors employing zirconia, one of the most promising gate dielectric. Samples were annealed in hydrogen ambient for up to 30 minutes at different temperatures ranging from room temperature to 400°C. C-V measurements were done after annealing at each temperature and the hysteresis width was calculated from the C-V curves. A minimum hysteresis width of ∼35 mV was observed on annealing the sample at 200°C confirming the excellent suitability of this dielectric

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

A Novel VSI- and CSI-Fed Dual Stator Induction Motor Drive Topology for Medium-Voltage Drive Applications

A new configuration is proposed for high-power induction motor drives. The induction machine is provided with two three-phase stator windings with their axes in line. One winding is designed for higher voltage and is meant to handle the main (active) power. The second winding is designed for lower voltage and is meant to carry the excitation (reactive) power. The excitation winding is powered by an insulated-gate-bipolar-transistor-based voltage source inverter with an output filter. The power winding is fed by a load-commutated current source inverter. The commutation of thyristors in the load-commutated inverter (LCI) is achieved by injecting the required leading reactive power from the excitation inverter. The MMF harmonics due to the LCI current are also cancelled out by injecting a suitable compensating component from the excitation inverter, so that the electromagnetic torque of the machine is smooth. Results from a prototype drive are presented to demonstrate the concept.

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization

With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read

In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose static noise margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and hold noise margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag- super-cut-off in stand-by mode without affecting its performance in active mode of operation. The read bit line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

An ultra-stable Cu nanowire under thermo-mechanical loading: A molecular dynamic study

We report on the formation of a stable Body-Centered Heptahedral (BCH) crystalline nanobridge structure of diameter ~ 1nm under high strain rate tensile loading to a <100> Cu nanowire. Extensive Molecular Dynamics (MD) simulations are performed. Six different cross-sectional dimensions of Cu nanowires are analyzed, i.e. 0.3615 x 0.3615 nm2, 0.723 x 0.723 nm2, 1.0845 x 1.0845 nm2, 1.446 x 1.446 nm2, 1.8075 x 1.8075 nm2, and 2.169 x 2.169 nm2. The strain rates used in the present simulations are 1 x 109 s-1, 1 x 108 s-1, and 1 x 107 s-1. We have shown that the length of the nanobridge can be characterized by larger plastic strain. A large plastic deformation is an indication that the structure is highly stable. The BCH nanobridge structure also shows enhanced mechanical properties such as higher fracture toughness and higher failure strain. The effect of temperature, strain rate and size of the nanowire on the formation of BCH structure is also explained in details. We also show that the initial orientation of the nanowires play an important role on the formation of BCH crystalline structure. Results indicate that proper tailoring of temperature and strain rate during processing or in the device can lead to very long BCH nanobridge structure of Cu with enhanced mechanical properties, which may find potential application for nano-scale electronic circuits.

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation

Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint. We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

Modified Stability Checking for On-Line Error Detection

The paper propose a unified error detection technique, based on stability checking, for on-line detection of delay, crosstalk and transient faults in combinational circuits and SEUs in sequential elements. The proposed method, called modified stability checking (MSC), overcomes the limitations of the earlier stability checking methods. The paper also proposed a novel checker circuit to realize this scheme. The checker is self-checking for a wide set of realistic internal faults including transient faults. Extensive circuit simulations have been done to characterize the checker circuit. A prototype checker circuit for a 1mm2 standard cell array has been implemented in a 0.13mum process.

Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which makes pass/fail determination on parts, resulting in significant test time and cost reduction.

Steady-State Stability of Current-Mode Active-Clamp ZVS DC-DC Converters

Active-clamp dc-dc converters are pulsewidth-modulated converters having two switches featuring zero-voltage switching at frequencies beyond 100 kHz. Generalized equivalent circuits valid for steady-state and dynamic performance have been proposed for the family of active-clamp converters. The active-clamp converter is analyzed for its dynamic behavior under current control in this paper. The steady-state stability analysis is presented. On account of the lossless damping inherent in the active-clamp converters, it appears that the stability region in the current-controlled active-clamp converters get extended for duty ratios, a little greater than 0.5 unlike in conventional hard-switched converters. The conventional graphical approach fails to assess the stability of current-controlled active-clamp converters, due to the coupling between the filter inductor current and resonant inductor current. An analysis that takes into account the presence of the resonant elements is presented to establish the condition for stability. This method correctly predicts the stability of the current-controlled active-clamp converters. A simple expression for the maximum duty cycle for subharmonic-free operation is obtained. The results are verified experimentally.

Nature of Electronic States in Atomically Thin MoS(2) Field-Effect Transistors

We present low-temperature electrical transport experiments in five field-effect transistor devices consisting of monolayer, bilayer, and trilayer MoS(2) films, mechanically exfoliated onto Si/SiO(2) substrate. Our experiments reveal that the electronic states In all films are localized well up to room temperature over the experimentally accessible range of gate voltage. This manifests in two-dimensional (2D) variable range hopping (VRH) at high temperatures, while below similar to 30 K, the conductivity displays oscillatory structures In gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T(0)) of VRH and gate voltage dependence of conductivity, we suggest that Coulomb potential from trapped charges In the substrate is the dominant source of disorder in MoS(2) field-effect devices, which leads to carrier localization, as well.