Application of electron beams in thermal processing of semiconductor materials and devices

Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.

Performance of CMOS Devices in Silicon-on-Sapphire Films After Solid-Phase Epitaxial Growth With Rapid Electron-Beam Heating

The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

Materials and devices toward three-dimensional integration

It has been shown that the apparent benefits of a two-layer stacked SOI system, i.e. packing density and speed improvements, are less than could be expected in the context of a VLSI requirement [1]. In this project the stacked SOI system has been identified as having major application in the realization of integrated, mixed technology systems. Zone-melting-recrystallization (ZMR) with lasers and electron beams have been used to produce device quality SOI material and a small test-bed circuit has been designed as a demonstration of the feasibility of this approach. © 1988.

Comment on 'processing and microstructure of single grain uranium-doped Y-Ba-Cu-O superconductor'

We comment on the paper by N Hari Babu et al. (2002 Supercond. Sci. Technol. 15 104-10) and point out misinterpretations of the chemical composition of U-bearing deposits observed in Y123. The observed small deposits are those of new compounds which do not contain Cu, rather than refined Y211 plus U, as stated by the authors. We further note that extensive literature, not quoted, is in disagreement by nearly an order of magnitude concerning the values of Pt and U doping at which the optimum value of Jc is obtained. Other related information, presently in the literature, which may be helpful to those working with this high temperature superconducting chemical system, is presented.