A novel vision chip for high-speed target tracking

This paper presents a novel vision chip for high-speed target tracking. Two concise algorithms for high-speed target tracking are developed. The algorithms include some basic operations that can be used to process the real-time image information during target tracking. The vision chip is implemented that is based on the algorithms and a row-parallel architecture. A prototype chip has 64 x 64 pixels is fabricated by 0.35 pm complementary metal-oxide-semiconductor transistor (CMOS) process with 4.5 x 2.5 mm(2) area. It operates at a rate of 1000 frames per second with 10 MHz chip main clock. The experiment results demonstrate that a high-speed target can be tracked in complex static background and a high-speed target among other high-speed objects can be tracked in clean background.

XPS depth profiling study of n/TCO interfaces for p-i-n amorphous silicon solar cells

Detailed X-ray photoelectron spectroscopy (XPS) depth profiling measurements were performed across the back n-layer/transparent conducting oxide (n/TCO) inter-faces for superstrate p-i-n solar cells to examine differences between amorphous silicon (a-Si:H) and microcrystalline silicon (mu c-Si:H) n-layer materials as well as TCO materials ZnO and ITO in the chemical, microstructural and diffusion properties of the back interfaces. No chemical reduction of TCO was found for all variations of n-layer/TCO interfaces. We found that n-a-Si:H interfaces better with ITO, while n-mu c-Si:H, with ZnO. A cross-comparison shows that the n-a-Si:H/ITO interface is superior to the n-mu c-Si:H/ZnO interface, as evidenced by the absence of oxygen segregation and less oxidized Si atoms observed near the interface together with much less diffusion of TCO into the n-layer. The results suggest that the n/TCO interface properties are correlated with the characteristics of both the n-layer and the TCO layer. Combined with the results reported on the device performance using similar back n/TCO contacts, we found the overall device performance may depend on both interface and bulk effects related to the back n/TCO contacts. (c) 2006 Elsevier B.V. All rights reserved.

Optical characteristics of DBR with inhomogeneous graded interfaces

Optical properties of Al0.9Ga0.1As/Al gamma Ga1-gamma As/GaAs/Al chi Ga1-chi As DBR with inhomogeneous graded interfaces has been investigated by using characteristic matrix method. The refractive index model and the analytic characteristic matrix of graded interfaces are obtained. The reflectance spectrum and the reflective phase shift are calculated for GaAs/Al-0.9 Ga-0.1 As DBR and graded interfaces DBR by using characteristic matrix method. The effect of graded interfaces on the optical properties of DBR is discussed. The result shows an extra graded phase matching layer must he added in front of the graded interfaces DBR to fulfil the conditions of phase matching at central wavelength. The accurate thickness of phase matching layer is calculated by optical thickness approximation method.

Interfaces in heterostructures of AlInGaN/GaN/Al2O3

Rutherford backscattering/channeling (RBS/C) and X-ray diffraction (XRD) are used to comprehensively characterize a heterostructure of AlInGaN/GaN/Al2O3(0001). The AlInGaN quaternary layer was revealed to process a high crystalline quality with a minimum yield of 1.4% from RBS/C measurements. The channeling spectrum of (1 (2) under bar 13) exhibits higher dechanneling than that of (0001) at the interface of AlInGaN/GaN. XRD measurements prove a coherent growth of AlInGaN on the GaN template layer. Combining RBS/C and XRD measurements, we found that the interface of GaN/Al2O3 is a nucleation layer, composed of a large amount of disorders and cubic GaN slabs, while the interface of AlInGaN/GaN is free of extra disordering (i.e. compare with the GaN layer). The conclusion is further evidenced by transmission electron microscopy (TEM). (c) 2005 Elsevier Ltd. All rights reserved.

New finite-difference scheme for simulations of step-index waveguides with tilt interfaces

A new finite-difference scheme is presented for the second derivative of a semivectorial field in a step-index optical waveguide with tilt interfaces. The present scheme provides an accurate description of the tilt interface of the nonrectangular structure. Comparison with previously presented formulas shows the effectiveness of the present scheme.

Radiative recombination characteristics in GaAs multilayer n(+)-i interfaces

In this communication, we have carried out a detailed investigation of radiative recombination in n-GaAs homojunction far-infrared detector structures with multilayer emitter (n(+))-intrinsic (i) interfaces by temperature-dependent steady-state photoluminescence measurements. The observation of the emitter-layer luminescence structures has been identified from their luminescence characteristics, in combination with high density theoretical calculation. A photogenerated carrier transferring model has been proposed, which can well explain the dependencies of the luminescence intensities on the laser excitation intensity and temperature. Furthermore, the obtained radiative recombination behavior helps us to offer a proposal to improve the operating temperature of the detector. (C) 2001 American Institute of Physics.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

Effect of rapid thermal annealing on Ti-AlN interfaces

The interface diffusion, reaction, and adherence of rapid thermal annealed Ti/ALN were investigated by RES, AES, SIMS, XRD and a scratch test. The experimental results show that diffusion and reaction occurs at the interface of Ti/AlN when the sample is rapidly annealed. During annealing, both the O adsorbed on the surface and doped in the AlN substrate diffuse into the Ti film. At low temperature TiO2 is produced. At higher temperature O reacts with the diffused Al in the Ti film and produces an Al2O3 layer in the middle of the film. N diffuses into the Ti film and produces TiN with an interface reaction. Ti oxide is produced at the interface between the film and the substrate. Scratch test results show that interface adherence is distinctly improved by rapid annealing at low temperature and decreases at higher temperature. (C) 1999 Elsevier Science B.V. All rights reserved.

Analysis of the interfaces of [NiFe/Mo](30) and [Fe/Mo](30) multilayers

The interface states of [NiFe/Mo](30) and [Fe/Mo](30) multilayers have been investigated by x-ray small angle reflection and diffuse scattering. Significant interface roughness correlation was observed in both ultrathin [NiFe/Mo](30) and [Fe/Mo](30) multilayers. An uncorrelated roughness of about 27-3.1 Angstrom was revealed in the [NiPe/Mo](30) multilayers, which is explained as originating from a transition layer between the NiFe and the Mo layers. By the technique of diffuse scattering, it is clearly indicated that the interfacial roughness of NiFe/Mo is much smaller than that of Fe/Mo although the lattice mismatch is the same in both multilayers.

A novel ultra low power temperature sensor for UHF RFID tag chip

A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs are not needed. The sensor is realized in a standard 0.18 mu m CMOS process, and the area is only 0.2mm(2). The accuracy of the temperature sensor is +/- 1 degrees C after calibration. The power consumption of the sensor is only 0.9 mu W.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

Neuro-Stimulus Chip with Photodiodes Array for Sub-retinal Implants

A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by Age-related Macular Degeneration (AMD) or Retinitis Pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safty. The prototype chip is designed and fabricated in HJTC 0.18 mu m N-well CMOS 1P6M Mix-signal process, with a +/- 2.5 V dual voltage power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Synthesis Tool for a Tile-Based Heterogeneous FPGA

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.