WTROPIC : um gerador automático de macro células CMOS acessível via WWW

Este trabalho apresenta a pesquisa e o desenvolvimento da ferramenta para geração automática de leiautes WTROPIC. O WTROPIC é uma ferramenta para a geração remota, acessível via WWW, de leiautes para circuitos CMOS adequada ao projeto FUCAS e ao ambiente CAVE. O WTROPIC foi concebido a partir de otimizações realizadas na versão 3 da ferramenta TROPIC. É mostrado também, como as otimizações no leiaute do TROPIC foram implementadas e como essas otimizações permitem ao WTROPIC cerca de 10% de redução da largura dos circuitos gerados em comparação ao TROPIC. Como o TROPIC, o WTROPIC é um gerador de macro células CMOS independente de biblioteca. Apresenta-se também, como a ferramenta WTROPIC foi integrada ao ambiente de concepção de circuitos CAVE, as mudanças propostas para metodologia de integração de ferramentas do CAVE que conduzem a uma melhora na qualidade de integração e a padronização das interfaces de usuário e como a síntese física de um leiaute pode ser então realizada remotamente. Dessa maneira, obteve-se uma ferramenta para a concepção de leiautes disponível a qualquer usuário com acesso a internet, mesmo que esse usuário não disponha de uma máquina com elevada capacidade de processamento, normalmente exigido por ferramentas de CAD.

Estimativa de capacitâncias e consumo de potência em circuitos combinacionais CMOS no nível lógico

Esta tese propõe o desenvolvimento de um método de estimativa de capacitâncias e de potência consumida nos circuitos combinacionais CMOS, no nível de portas lógicas. O objetivo do método é fazer uma previsão do consumo de potência do circuito na fase de projeto lógico, o que permitirá a aplicação de técnicas de redução de potência ou até alteração do projeto antes da geração do seu leiaute. A potência dinâmica consumida por circuitos CMOS depende dos seguintes parâmetros: tensão de alimentação, freqüência de operação, capacitâncias parasitas e atividades de comutação em cada nodo do circuito. A análise desenvolvida na Tese, propõe que a potência seja dividida em duas componentes. A primeira componente está relacionada ao consumo de potência devido às capacitâncias intrínsecas dos transistores, que por sua vez estão relacionadas às dimensões dos transistores. Estas capacitâncias intrínsecas são concentradas nos nodos externos das portas e manifestam-se em função das combinações dos vetores de entrada. A segunda componente está relacionada às interconexões entre as células do circuito. Para esta etapa utiliza-se a estimativa do comprimento médio das interconexões e as dimensões tecnológicas para estimar o consumo de potência. Este comprimento médio é estimado em função do número de transistores e fanout das várias redes do circuito. Na análise que trata das capacitâncias intrínsecas dos transistores os erros encontrados na estimativa da potência dissipada estão no máximo em torno de 11% quando comparados ao SPICE. Já na estimativa das interconexões a comparação feita entre capacitâncias de interconexões estimadas no nível lógico e capacitâncias de interconexões extraídas do leiaute apresentou erros menores que 10%.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

A consumption CAPM with a reference level

We study an intertemporal asset pricing model in which a representative consumer maximizes expected utility derived from both the ratio of his consumption to some reference level and this level itself. If the reference consumption level is assumed to be determined by past consumption levels, the model generalizes the usual habit formation specifications. When the reference level growth rate is made dependent on the market portfolio return and on past consumption growth, the model mixes a consumption CAPM with habit formation together with the CAPM. It therefore provides, in an expected utility framework, a generalization of the non-expected recursive utility model of Epstein and Zin (1989). When we estimate this specification with aggregate per capita consumption, we obtain economically plausible values of the preference parameters, in contrast with the habit formation or the Epstein-Zin cases taken separately. All tests performed with various preference specifications confirm that the reference level enters significantly in the pricing kernel.

Design of boundary-scan testing in CMOS image sensors for industrial applications: internship repor

Tests on printed circuit boards and integrated circuits are widely used in industry,resulting in reduced design time and cost of a project. The functional and connectivity tests in this type of circuits soon began to be a concern for the manufacturers, leading to research for solutions that would allow a reliable, quick, cheap and universal solution. Initially, using test schemes were based on a set of needles that was connected to inputs and outputs of the integrated circuit board (bed-of-nails), to which signals were applied, in order to verify whether the circuit was according to the specifications and could be assembled in the production line. With the development of projects, circuit miniaturization, improvement of the production processes, improvement of the materials used, as well as the increase in the number of circuits, it was necessary to search for another solution. Thus Boundary-Scan Testing was developed which operates on the border of integrated circuits and allows testing the connectivity of the input and the output ports of a circuit. The Boundary-Scan Testing method was converted into a standard, in 1990, by the IEEE organization, being known as the IEEE 1149.1 Standard. Since then a large number of manufacturers have adopted this standard in their products. This master thesis has, as main objective: the design of Boundary-Scan Testing in an image sensor in CMOS technology, analyzing the standard requirements, the process used in the prototype production, developing the design and layout of Boundary-Scan and analyzing obtained results after production. Chapter 1 presents briefly the evolution of testing procedures used in industry, developments and applications of image sensors and the motivation for the use of architecture Boundary-Scan Testing. Chapter 2 explores the fundamentals of Boundary-Scan Testing and image sensors, starting with the Boundary-Scan architecture defined in the Standard, where functional blocks are analyzed. This understanding is necessary to implement the design on an image sensor. It also explains the architecture of image sensors currently used, focusing on sensors with a large number of inputs and outputs.Chapter 3 describes the design of the Boundary-Scan implemented and starts to analyse the design and functions of the prototype, the used software, the designs and simulations of the functional blocks of the Boundary-Scan implemented. Chapter 4 presents the layout process used based on the design developed on chapter 3, describing the software used for this purpose, the planning of the layout location (floorplan) and its dimensions, the layout of individual blocks, checks in terms of layout rules, the comparison with the final design and finally the simulation. Chapter 5 describes how the functional tests were performed to verify the design compliancy with the specifications of Standard IEEE 1149.1. These tests were focused on the application of signals to input and output ports of the produced prototype. Chapter 6 presents the conclusions that were taken throughout the execution of the work.

Reference evapotranspiration estimation inside greenhouses

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Haematological and biochemical reference intervals for farmed channel catfish

The reference intervals for biochemical variables and red blood cell indices of healthy intensively bred channel catfish Ictalurus punctatus were determined. The blood variables were determined using standardized clinical methods. The reference intervals (25th and 75th percentiles) were established using a non-parametric method. Reference intervals for plasma glucose, serum total protein, sodium, potassium, calcium, magnesium, chloride concentration, primary and secondary red blood cell indices were established. The haematological and biochemical reference intervals established may allow important clinical decisions about channel catfish. (c) 2007 the Authors Journal compilation (C) 2007 the Fisheries Society of the British Isles.

Selection and validation of reference genes for gene expression studies by reverse transcription quantitative PCR in Xanthomonas citri subsp citri during infection of Citrus sinensis

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Controle Adaptativo Robusto para Filtros Ativos de Potência Paralelo

Conventional control strategies used in shunt active power filters (SAPF) employs real-time instantaneous harmonic detection schemes which is usually implements with digital filters. This increase the number of current sensors on the filter structure which results in high costs. Furthermore, these detection schemes introduce time delays which can deteriorate the harmonic compensation performance. Differently from the conventional control schemes, this paper proposes a non-standard control strategy which indirectly regulates the phase currents of the power mains. The reference currents of system are generated by the dc-link voltage controller and is based on the active power balance of SAPF system. The reference currents are aligned to the phase angle of the power mains voltage vector which is obtained by using a dq phase locked loop (PLL) system. The current control strategy is implemented by an adaptive pole placement control strategy integrated to a variable structure control scheme (VS-APPC). In the VS-APPC, the internal model principle (IMP) of reference currents is used for achieving the zero steady state tracking error of the power system currents. This forces the phase current of the system mains to be sinusoidal with low harmonics content. Moreover, the current controllers are implemented on the stationary reference frame to avoid transformations to the mains voltage vector reference coordinates. This proposed current control strategy enhance the performance of SAPF with fast transient response and robustness to parametric uncertainties. Experimental results are showing for determining the effectiveness of SAPF proposed control system

VCO Banda Larga Integrado para Receptor a Cinco Portas

This work presents an wideband ring VCO for cognitive radio five-port based receivers. A three-stage differential topology using transmission gate was adopted in order to maintain wide and linear tuning range and a low phase-noise. Monte-Carlo analysis were performed for phase-shift response of individual stages, which is an important figure of merit in five-port works. It was observed a fairly linear correlation between control voltage and oscillation frequency in the range between 200 MHz and 1800 MHz. The VCO was preliminarily designed for IBM 130nm CMOS technology

Estratégia de controle robusto para filtro ativo paralelo sem detecção de harmônicos de correntes

Conventional control strategies used in shunt active power filters (SAPF) employs real-time instantaneous harmonic detection schemes which is usually implements with digital filters. This increase the number of current sensors on the filter structure which results in high costs. Furthermore, these detection schemes introduce time delays which can deteriorate the harmonic compensation performance. Differently from the conventional control schemes, this paper proposes a non-standard control strategy which indirectly regulates the phase currents of the power mains. The reference currents of system are generated by the dc-link voltage controller and is based on the active power balance of SAPF system. The reference currents are aligned to the phase angle of the power mains voltage vector which is obtained by using a dq phase locked loop (PLL) system. The current control strategy is implemented by an adaptive pole placement control strategy integrated to a variable structure control scheme (VS¡APPC). In the VS¡APPC, the internal model principle (IMP) of reference currents is used for achieving the zero steady state tracking error of the power system currents. This forces the phase current of the system mains to be sinusoidal with low harmonics content. Moreover, the current controllers are implemented on the stationary reference frame to avoid transformations to the mains voltage vector reference coordinates. This proposed current control strategy enhance the performance of SAPF with fast transient response and robustness to parametric uncertainties. Experimental results are showing for determining the effectiveness of SAPF proposed control system

Maximização da penetração da geração distribuída através do algoritmo de otimização nuvem de partículas

This work develops a methodology for defining the maximum active power being injected into predefined nodes in the studied distribution networks, considering the possibility of multiple accesses of generating units. The definition of these maximum values is obtained from an optimization study, in which further losses should not exceed those of the base case, i.e., without the presence of distributed generation. The restrictions on the loading of the branches and voltages of the system are respected. To face the problem it is proposed an algorithm, which is based on the numerical method called particle swarm optimization, applied to the study of AC conventional load flow and optimal load flow for maximizing the penetration of distributed generation. Alternatively, the Newton-Raphson method was incorporated to resolution of the load flow. The computer program is performed with the SCILAB software. The proposed algorithm is tested with the data from the IEEE network with 14 nodes and from another network, this one from the Rio Grande do Norte State, at a high voltage (69 kV), with 25 nodes. The algorithm defines allowed values of nominal active power of distributed generation, in percentage terms relative to the demand of the network, from reference values

New constraints on ages of glasses proposed as reference materials for fission-track dating

New analyses have been performed in order to enhance the data-set on the independent ages of four glasses that have been proposed as reference materials for fission-track dating. The results are as follows. Moldavite - repeated (40)Ar/(39)Ar age determinations on samples from deposits from Bohemia and Moravia yielded an average of 14.34 +/- 0.08 Ma. This datum agrees with other recent determinations and is significantly younger than the (40)Ar/(39)Ar age of 15.21 +/- 0.15 Ma determined in the early 1980s. Macusanite (Peru) -four K-Ar ages ranging from 5.44 +/- 0.06 to 5.72 +/- 0.12 Ma have been published previously. New (40)Ar/(39)Ar ages gave an average of 5.12 +/- 0.04 Ma. Plateau fission-track ages determined using the IRMM-540 certified glass and U and Th thin films for neutron fluence measurements agree better with these new (40)Ar/(39)Ar ages than the previously published ages. Roccastrada glass (Italy) - a new (40)Ar/(39)Ar age, 2.45 +/- 0.04 Ma, is consistent with previous determinations. The Quiron obsidian (Argentina) is a recently discovered glass that has been proposed as an additional reference material for its high spontaneous track density (around 100 000 cm(-2)). Defects that might produce spurious tracks are virtually absent. An independent (40)Ar/(39)Ar age of 8.77 +/- 0.09 Ma was determined and is recommended for this glass. We believe that these materials, which will be distributed upon request to fission-track groups, will be very useful for testing system calibrations and experimental procedures.

Electron spin resonance of Gd3+ in the antiferromagnetic heavy fermion CeIn3 and its reference compound LaIn3

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)