982 resultados para topological insulator


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In ultracold atoms settings, inelastic light scattering is a preeminent technique to reveal static and dynamic properties at nonzero momentum. In this work, we investigate an array of one-dimensional trapped Bose gases, by measuring both the energy and the momentum imparted to the system via light scattering experiments. The measurements are performed in the weak perturbation regime, where these two quantities-the energy and momentum transferred-are expected to be related to the dynamic structure factor of the system. We discuss this relation, with special attention to the role of in-trap dynamics on the transferred momentum.

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The main goal of this work is to give the reader a basic introduction into the subject of topological groups, bringing together the areas of topology and group theory.

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A possibilidade da existência de átomos de hidrogênio estáveis em dimensões superiores a três é abordada. O problema da dimensionalidade é visto como um problema de Física, no qual relacionam-se algumas leis físicas com a dimensão espacial. A base da análise deste trabalho faz uso das equações de Schrödinger (não relativística) e de Dirac (relativística). Nos dois casos, utiliza-se a generalização tanto do setor cinemático bem como o setor de interação coulombiana para variar o parâmetro topológico dimensão. Para o caso não relativístico, os auto-valores de energia e as auto-funções são obtidas através do método numérico de Numerov. Embora existam soluções em espaços com dimensões superiores, os resultados obtidos no presente trabalho indicam que a natureza deve, de alguma maneira, se manifestar em um espaço tridimensional.

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An ingenious new CMOS-compatible process which promises to significantly improve the performance of power devices is discussed. A novel power device concept based on the use of high voltage regions suspended on thin semiconductor/dielectric membranes is reported. The membrane power devices are manufactured in a fully-CMOS compatible silicon-on-insulator (SOI) process followed by a bulk etching step and subsequent back-passivation. The concept is applicable to a class of high voltage devices such as LDMOSFETs, diodes, LIGBTs and superjunctions.

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We demonstrate that the Mott metal-insulator transition (MIT) in single crystalline VO(2) nanowires is strongly mediated by surface stress as a consequence of the high surface area to volume ratio of individual nanowires. Further, we show that the stress-induced antiferromagnetic Mott insulating phase is critical in controlling the spatial extent and distribution of the insulating monoclinic and metallic rutile phases as well as the electrical characteristics of the Mott transition. This affords an understanding of the relationship between the structural phase transition and the Mott MIT.

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A pivotal problem in Bayesian nonparametrics is the construction of prior distributions on the space M(V) of probability measures on a given domain V. In principle, such distributions on the infinite-dimensional space M(V) can be constructed from their finite-dimensional marginals---the most prominent example being the construction of the Dirichlet process from finite-dimensional Dirichlet distributions. This approach is both intuitive and applicable to the construction of arbitrary distributions on M(V), but also hamstrung by a number of technical difficulties. We show how these difficulties can be resolved if the domain V is a Polish topological space, and give a representation theorem directly applicable to the construction of any probability distribution on M(V) whose first moment measure is well-defined. The proof draws on a projective limit theorem of Bochner, and on properties of set functions on Polish spaces to establish countable additivity of the resulting random probabilities.

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Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.

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Hydrogenated amorphous silicon (a-Si:H) thin films have been deposited from silane using a novel photo-enhanced decomposition technique. The system comprises a hydrogen discharge lamp contained within the reaction vessel; this unified approach allows high energy photon excitation of the silane molecules without absorption by window materials or the need for mercury sensitisation. The film growth rates (exceeding 4 Angstrom/s) and material properties obtained are comparable to those of films produced by plasma-enhanced CVD techniques. The reduction of energetic charged particles in the film growth region should enable the fabrication of cleaner semiconductor/insulator interfaces in thin-film transistors.

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This paper investigates the variation of the integrated density of states with conduction activation energy in hydrogenated amorphous silicon thin film transistors. Results are given for two different gate insulator layers, PECVD silicon oxide and thermally grown silicon dioxide. The different gate insulators produce transistors with very different initial transfer characteristics, but the variation of integrated density of states with conduction activation energy is shown to be similar.

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To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

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In the field of flat panel displays, the current leading technology is the Active Matrix liquid Crystal Display; this uses a-Si:H based thin film transistors (TFTs) as the switching element in each pixel. However, under gate bias a-Si:H TFTs suffer from instability, as is evidenced by a shift in the gate threshold voltage. The shift in the gate threshold voltage is generally measured from the gate transfer characteristics, after subjecting the TFT to prolonged gate bias. However, a major drawback of this measurement method is that it cannot distinguish whether the shift is caused by the change in the midgap states in the a-Si:H channel or by charge trapping in the gate insulator. In view of this, we have developed a capacitance-voltage (C-V) method to measure the shift in threshold voltage. We employ Metal-Insulator-Semiconductor (MIS) structures to investigate the threshold voltage shift as they are simpler to fabricate than TFTs. We have investigated a large of number Metal/a-Si:H/Si3N4/Si+n structures using our C-V technique. From, the C-V data for the MIS structures, we have found that the relationship between the thermal energy and threshold voltage shift is similar to that reported by Wehrspohn et. al in a-Si:H TFTs (J Appl. Phys, 144, 87, 2000). The a-Si:H and Si3N4 layers were grown using the radio-frequency plasma-enhanced chemical vapour deposition technique.

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Smart chemical sensor based on CMOS(complementary metal-oxide- semiconductor) compatible SOI(silicon on insulator) microheater platform was realized by facilitating ZnO nanowires growth on the small membrane at the relatively low temperature. Our SOI microheater platform can be operated at the very low power consumption with novel metal oxide sensing materials, like ZnO or SnO2 nanostructured materials which demand relatively high sensing temperature. In addition, our sol-gel growth method of ZnO nanowires on the SOI membrane was found to be very effective compared with ink-jetting or CVD growth techniques. These combined techniques give us the possibility of smart chemical sensor technology easily merged into the conventional semiconductor IC application. The physical properties of ZnO nanowire network grown by the solution-based method and its chemical sensing property also were reported in this paper.

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This paper investigates the performance of diode temperature sensors when operated at ultra high temperatures (above 250°C). A low leakage Silicon On Insulator (SOI) diode was designed and fabricated in a 1 μm CMOS process and suspended within a dielectric membrane for efficient thermal insulation. The diode can be used for accurate temperature monitoring in a variety of sensors such as microcalorimeters, IR detectors, or thermal flow sensors. A CMOS compatible micro-heater was integrated with the diode for local heating. It was found that the diode forward voltage exhibited a linear dependence on temperature as long as the reverse saturation current remained below the forward driving current. We have proven experimentally that the maximum temperature can be as high as 550°C. Long term continuous operation at high temperatures (400°C) showed good stability of the voltage drop. Furthermore, we carried out a detailed theoretical analysis to determine the maximum operating temperature and exlain the presence of nonlinearity factors at ultra high temperatures. © 2008 IEEE.

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The successful utilization of an array of silicon on insulator complementary metal oxide semiconductor (SOICMOS) micro thermal shear stress sensors for flow measurements at macro-scale is demonstrated. The sensors use CMOS aluminum metallization as the sensing material and are embedded in low thermal conductivity silicon oxide membranes. They have been fabricated using a commercial 1 μm SOI-CMOS process and a post-CMOS DRIE back etch. The sensors with two different sizes were evaluated. The small sensors (18.5 ×18.5 μm2 sensing area on 266 × 266 μm2 oxide membrane) have an ultra low power (100 °C temperature rise at 6mW) and a small time constant of only 5.46 μs which corresponds to a cut-off frequency of 122 kHz. The large sensors (130 × 130 μm2 sensing area on 500 × 500 μm2 membrane) have a time constant of 9.82 μs (cut-off frequency of 67.9 kHz). The sensors' performance has proven to be robust under transonic and supersonic flow conditions. Also, they have successfully identified laminar, separated, transitional and turbulent boundary layers in a low speed flow. © 2008 IEEE.