Improvement of the Dynamic Performance of a Multiphase Current Controlled Buck Converter using an Auxiliary Synchronous Buck Converter as an Additional Energy Path

This work is related to the output impedance improvement of a Multiphase Buck converter with Peak Current Mode Control (PCMC) by means of introducing an additional power path that virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a Single Phase Buck converter with Voltage Mode Control (VMC), while in the VRM applications, due to the high currents, the system is usually implemented as a Multiphase Buck Converter with Current Mode Control. The additional energy path, as presented here, is introduced with the Output Impedance Correction Circuit (OICC) based on the Controlled Current Source (CCS). The OICC is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, this work extends the OICC concept to a Multiphase Buck Converter system while comparing proposed solution with the system that has n times bigger output capacitor. In addition, the OICC is implemented as a Synchronous Buck Converter with PCMC, thus reducing its influence on the system efficiency.

Aerial Coverage Path Planning applied to Mapping

In the last decade we have seen how small and light weight aerial platforms - aka, Mini Unmanned Aerial Vehicles (MUAV) - shipped with heterogeneous sensors have become a 'most wanted' Remote Sensing (RS) tool. Most of the off-the-shelf aerial systems found in the market provide way-point navigation. However, they do not rely on a tool that compute the aerial trajectories considering all the aspects that allow optimizing the aerial missions. One of the most demanded RS applications of MUAV is image surveying. The images acquired are typically used to build a high-resolution image, i.e., a mosaic of the workspace surface. Although, it may be applied to any other application where a sensor-based map must be computed. This thesis provides a study of this application and a set of solutions and methods to address this kind of aerial mission by using a fleet of MUAVs. In particular, a set of algorithms are proposed for map-based sampling, and aerial coverage path planning (ACPP). Regarding to map-based sampling, the approaches proposed consider workspaces with different shapes and surface characteristics. The workspace is sampled considering the sensor characteristics and a set of mission requirements. The algorithm applies different computational geometry approaches, providing a unique way to deal with workspaces with different shape and surface characteristics in order to be surveyed by one or more MUAVs. This feature introduces a previous optimization step before path planning. After that, the ACPP problem is theorized and a set of ACPP algorithms to compute the MUAVs trajectories are proposed. The problem addressed herein is the problem to coverage a wide area by using MUAVs with limited autonomy. Therefore, the mission must be accomplished in the shortest amount of time. The aerial survey is usually subject to a set of workspace restrictions, such as the take-off and landing positions as well as a safety distance between elements of the fleet. Moreover, it has to avoid forbidden zones to y. Three different algorithms have been studied to address this problem. The approaches studied are based on graph searching, heuristic and meta-heuristic approaches, e.g., mimic, evolutionary. Finally, an extended survey of field experiments applying the previous methods, as well as the materials and methods adopted in outdoor missions is presented. The reported outcomes demonstrate that the findings attained from this thesis improve ACPP mission for mapping purpose in an efficient and safe manner.

Aerial Coverage Path Planning applied to Mapping

In the last decade we have seen how small and light weight aerial platforms - aka, Mini Unmanned Aerial Vehicles (MUAV) - shipped with heterogeneous sensors have become a 'most wanted' Remote Sensing (RS) tool. Most of the off-the-shelf aerial systems found in the market provide way-point navigation. However, they do not rely on a tool that compute the aerial trajectories considering all the aspects that allow optimizing the aerial missions. One of the most demanded RS applications of MUAV is image surveying. The images acquired are typically used to build a high-resolution image, i.e., a mosaic of the workspace surface. Although, it may be applied to any other application where a sensor-based map must be computed. This thesis provides a study of this application and a set of solutions and methods to address this kind of aerial mission by using a fleet of MUAVs. In particular, a set of algorithms are proposed for map-based sampling, and aerial coverage path planning (ACPP). Regarding to map-based sampling, the approaches proposed consider workspaces with different shapes and surface characteristics. The workspace is sampled considering the sensor characteristics and a set of mission requirements. The algorithm applies different computational geometry approaches, providing a unique way to deal with workspaces with different shape and surface characteristics in order to be surveyed by one or more MUAVs. This feature introduces a previous optimization step before path planning. After that, the ACPP problem is theorized and a set of ACPP algorithms to compute the MUAVs trajectories are proposed. The problem addressed herein is the problem to coverage a wide area by using MUAVs with limited autonomy. Therefore, the mission must be accomplished in the shortest amount of time. The aerial survey is usually subject to a set of workspace restrictions, such as the take-off and landing positions as well as a safety distance between elements of the fleet. Moreover, it has to avoid forbidden zones to y. Three different algorithms have been studied to address this problem. The approaches studied are based on graph searching, heuristic and meta-heuristic approaches, e.g., mimic, evolutionary. Finally, an extended survey of field experiments applying the previous methods, as well as the materials and methods adopted in outdoor missions is presented. The reported outcomes demonstrate that the findings attained from this thesis improve ACPP mission for mapping purpose in an efficient and safe manner.

Output Impedance Correction Circuit (OICC): A New Concept to Improve the Dynamic Response of DC/DC Converters with Additional Energy Path

El desarrollo da las nuevas tecnologías permite a los ingenieros llevar al límite el funcionamiento de los circuitos integrados (Integrated Circuits, IC). Las nuevas generaciones de procesadores, DSPs o FPGAs son capaces de procesar la información a una alta velocidad, con un alto consumo de energía, o esperar en modo de baja potencia con el mínimo consumo posible. Esta gran variación en el consumo de potencia y el corto tiempo necesario para cambiar de un nivel al otro, afecta a las especificaciones del Módulo de Regulador de Tensión (Voltage Regulated Module, VRM) que alimenta al IC. Además, las características adicionales obligatorias, tales como adaptación del nivel de tensión (Adaptive Voltage Positioning, AVP) y escalado dinámico de la tensión (Dynamic Voltage Scaling, DVS), imponen requisitos opuestas en el diseño de la etapa de potencia del VRM. Para poder soportar las altas variaciones de los escalones de carga, el condensador de filtro de salida del VRM se ha de sobredimensionar, penalizando la densidad de energía y el rendimiento durante la operación de DVS. Por tanto, las actuales tendencias de investigación se centran en mejorar la respuesta dinámica del VRM, mientras se reduce el tamaño del condensador de salida. La reducción del condensador de salida lleva a menor coste y una prolongación de la vida del sistema ya que se podría evitar el uso de condensadores voluminosos, normalmente implementados con condensadores OSCON. Una ventaja adicional es que reduciendo el condensador de salida, el DVS se puede realizar más rápido y con menor estrés de la etapa de potencia, ya que la cantidad de carga necesaria para cambiar la tensión de salida es menor. El comportamiento dinámico del sistema con un control lineal (Control Modo Tensión, VMC, o Control Corriente de Pico, Peak Current Mode Control, PCMC,…) está limitado por la frecuencia de conmutación del convertidor y por el tamaño del filtro de salida. La reducción del condensador de salida se puede lograr incrementando la frecuencia de conmutación, así como incrementando el ancho de banda del sistema, y/o aplicando controles avanzados no-lineales. Usando esos controles, las variables del estado se saturan para conseguir el nuevo régimen permanente en un tiempo mínimo, así como el filtro de salida, más específicamente la pendiente de la corriente de la bobina, define la respuesta de la tensión de salida. Por tanto, reduciendo la inductancia de la bobina de salida, la corriente de bobina llega más rápido al nuevo régimen permanente, por lo que una menor cantidad de carga es tomada del condensador de salida durante el tránsito. El inconveniente de esa propuesta es que el rendimiento del sistema es penalizado debido al incremento de pérdidas de conmutación y las corrientes RMS. Para conseguir tanto la reducción del condensador de salida como el alto rendimiento del sistema, mientras se satisfacen las estrictas especificaciones dinámicas, un convertidor multifase es adoptado como estándar para aplicaciones VRM. Para asegurar el reparto de las corrientes entre fases, el convertidor multifase se suele implementar con control de modo de corriente. Para superar la limitación impuesta por el filtro de salida, la segunda posibilidad para reducir el condensador de salida es aplicar alguna modificación topológica (Topologic modifications) de la etapa básica de potencia para incrementar la pendiente de la corriente de bobina y así reducir la duración de tránsito. Como el transitorio se ha reducido, una menor cantidad de carga es tomada del condensador de salida bajo el mismo escalón de la corriente de salida, con lo cual, el condensador de salida se puede reducir para lograr la misma desviación de la tensión de salida. La tercera posibilidad para reducir el condensador de salida del convertidor es introducir un camino auxiliar de energía (additional energy path, AEP) para compensar el desequilibrio de la carga del condensador de salida reduciendo consecuentemente la duración del transitorio y la desviación de la tensión de salida. De esta manera, durante el régimen permanente, el sistema tiene un alto rendimiento debido a que el convertidor principal con bajo ancho de banda es diseñado para trabajar con una frecuencia de conmutación moderada para conseguir requisitos estáticos. Por otro lado, el comportamiento dinámico durante los transitorios es determinado por el AEP con un alto ancho de banda. El AEP puede ser implementado como un camino resistivo, como regulador lineal (Linear regulator, LR) o como un convertidor conmutado. Las dos primeras implementaciones proveen un mayor ancho de banda, acosta del incremento de pérdidas durante el transitorio. Por otro lado, la implementación del convertidor computado presenta menor ancho de banda, limitado por la frecuencia de conmutación, aunque produce menores pérdidas comparado con las dos anteriores implementaciones. Dependiendo de la aplicación, la implementación y la estrategia de control del sistema, hay una variedad de soluciones propuestas en el Estado del Arte (State-of-the-Art, SoA), teniendo diferentes propiedades donde una solución ofrece más ventajas que las otras, pero también unas desventajas. En general, un sistema con AEP ideal debería tener las siguientes propiedades: 1. El impacto del AEP a las pérdidas del sistema debería ser mínimo. A lo largo de la operación, el AEP genera pérdidas adicionales, con lo cual, en el caso ideal, el AEP debería trabajar por un pequeño intervalo de tiempo, solo durante los tránsitos; la otra opción es tener el AEP constantemente activo pero, por la compensación del rizado de la corriente de bobina, se generan pérdidas innecesarias. 2. El AEP debería ser activado inmediatamente para minimizar la desviación de la tensión de salida. Para conseguir una activación casi instantánea, el sistema puede ser informado por la carga antes del escalón o el sistema puede observar la corriente del condensador de salida, debido a que es la primera variable del estado que actúa a la perturbación de la corriente de salida. De esa manera, el AEP es activado con casi cero error de la tensión de salida, logrando una menor desviación de la tensión de salida. 3. El AEP debería ser desactivado una vez que el nuevo régimen permanente es detectado para evitar los transitorios adicionales de establecimiento. La mayoría de las soluciones de SoA estiman la duración del transitorio, que puede provocar un transitorio adicional si la estimación no se ha hecho correctamente (por ejemplo, si la corriente de bobina del convertidor principal tiene un nivel superior o inferior al necesitado, el regulador lento del convertidor principal tiene que compensar esa diferencia una vez que el AEP es desactivado). Otras soluciones de SoA observan las variables de estado, asegurando que el sistema llegue al nuevo régimen permanente, o pueden ser informadas por la carga. 4. Durante el transitorio, como mínimo un subsistema, o bien el convertidor principal o el AEP, debería operar en el lazo cerrado. Implementando un sistema en el lazo cerrado, preferiblemente el subsistema AEP por su ancho de banda elevado, se incrementa la robustez del sistema a los parásitos. Además, el AEP puede operar con cualquier tipo de corriente de carga. Las soluciones que funcionan en el lazo abierto suelen preformar el control de balance de carga con mínimo tiempo, así reducen la duración del transitorio y tienen un impacto menor a las pérdidas del sistema. Por otro lado, esas soluciones demuestran una alta sensibilidad a las tolerancias y parásitos de los componentes. 5. El AEP debería inyectar la corriente a la salida en una manera controlada, así se reduce el riesgo de unas corrientes elevadas y potencialmente peligrosas y se incrementa la robustez del sistema bajo las perturbaciones de la tensión de entrada. Ese problema suele ser relacionado con los sistemas donde el AEP es implementado como un convertidor auxiliar. El convertidor auxiliar es diseñado para una potencia baja, con lo cual, los dispositivos elegidos son de baja corriente/potencia. Si la corriente no es controlada, bajo un pico de tensión de entrada provocada por otro parte del sistema (por ejemplo, otro convertidor conectado al mismo bus), se puede llegar a un pico en la corriente auxiliar que puede causar la perturbación de tensión de salida e incluso el fallo de los dispositivos del convertidor auxiliar. Sin embargo, cuando la corriente es controlada, usando control del pico de corriente o control con histéresis, la corriente auxiliar tiene el control con prealimentación (feed-forward) de tensión de entrada y la corriente es definida y limitada. Por otro lado, si la solución utiliza el control de balance de carga, el sistema puede actuar de forma deficiente si la tensión de entrada tiene un valor diferente del nominal, provocando que el AEP inyecta/toma más/menos carga que necesitada. 6. Escalabilidad del sistema a convertidores multifase. Como ya ha sido comentado anteriormente, para las aplicaciones VRM por la corriente de carga elevada, el convertidor principal suele ser implementado como multifase para distribuir las perdidas entre las fases y bajar el estrés térmico de los dispositivos. Para asegurar el reparto de las corrientes, normalmente un control de modo corriente es usado. Las soluciones de SoA que usan VMC son limitadas a la implementación con solo una fase. Esta tesis propone un nuevo método de control del flujo de energía por el AEP y el convertidor principal. El concepto propuesto se basa en la inyección controlada de la corriente auxiliar al nodo de salida donde la amplitud de la corriente es n-1 veces mayor que la corriente del condensador de salida con las direcciones apropiadas. De esta manera, el AEP genera un condensador virtual cuya capacidad es n veces mayor que el condensador físico y reduce la impedancia de salida. Como el concepto propuesto reduce la impedancia de salida usando el AEP, el concepto es llamado Output Impedance Correction Circuit (OICC) concept. El concepto se desarrolla para un convertidor tipo reductor síncrono multifase con control modo de corriente CMC (incluyendo e implementación con una fase) y puede operar con la tensión de salida constante o con AVP. Además, el concepto es extendido a un convertidor de una fase con control modo de tensión VMC. Durante la operación, el control de tensión de salida de convertidor principal y control de corriente del subsistema OICC están siempre cerrados, incrementando la robustez a las tolerancias de componentes y a los parásitos del cirquito y permitiendo que el sistema se pueda enfrentar a cualquier tipo de la corriente de carga. Según el método de control propuesto, el sistema se puede encontrar en dos estados: durante el régimen permanente, el sistema se encuentra en el estado Idle y el subsistema OICC esta desactivado. Por otro lado, durante el transitorio, el sistema se encuentra en estado Activo y el subsistema OICC está activado para reducir la impedancia de salida. El cambio entre los estados se hace de forma autónoma: el sistema entra en el estado Activo observando la corriente de condensador de salida y vuelve al estado Idle cunado el nuevo régimen permanente es detectado, observando las variables del estado. La validación del concepto OICC es hecha aplicándolo a un convertidor tipo reductor síncrono con dos fases y de 30W cuyo condensador de salida tiene capacidad de 140μF, mientras el factor de multiplicación n es 15, generando en el estado Activo el condensador virtual de 2.1mF. El subsistema OICC es implementado como un convertidor tipo reductor síncrono con PCMC. Comparando el funcionamiento del convertidor con y sin el OICC, los resultados demuestran que se ha logrado una reducción de la desviación de tensión de salida con factor 12, tanto con funcionamiento básico como con funcionamiento AVP. Además, los resultados son comparados con un prototipo de referencia que tiene la misma etapa de potencia y un condensador de salida físico de 2.1mF. Los resultados demuestran que los dos sistemas tienen el mismo comportamiento dinámico. Más aun, se ha cuantificado el impacto en las pérdidas del sistema operando bajo una corriente de carga pulsante y bajo DVS. Se demuestra que el sistema con OICC mejora el rendimiento del sistema, considerando las pérdidas cuando el sistema trabaja con la carga pulsante y con DVS. Por lo último, el condensador de salida de sistema con OICC es mucho más pequeño que el condensador de salida del convertidor de referencia, con lo cual, por usar el concepto OICC, la densidad de energía se incrementa. En resumen, las contribuciones principales de la tesis son: • El concepto propuesto de Output Impedance Correction Circuit (OICC), • El control a nivel de sistema basado en el método usado para cambiar los estados de operación, • La implementación del subsistema OICC en lazo cerrado conjunto con la implementación del convertidor principal, • La cuantificación de las perdidas dinámicas bajo la carga pulsante y bajo la operación DVS, y • La robustez del sistema bajo la variación del condensador de salida y bajo los escalones de carga consecutiva. ABSTRACT Development of new technologies allows engineers to push the performance of the integrated circuits to its limits. New generations of processors, DSPs or FPGAs are able to process information with high speed and high consumption or to wait in low power mode with minimum possible consumption. This huge variation in power consumption and the short time needed to change from one level to another, affect the specifications of the Voltage Regulated Module (VRM) that supplies the IC. Furthermore, additional mandatory features, such as Adaptive Voltage Positioning (AVP) and Dynamic Voltage Scaling (DVS), impose opposite trends on the design of the VRM power stage. In order to cope with high load-step amplitudes, the output capacitor of the VRM power stage output filter is drastically oversized, penalizing power density and the efficiency during the DVS operation. Therefore, the ongoing research trend is directed to improve the dynamic response of the VRM while reducing the size of the output capacitor. The output capacitor reduction leads to a smaller cost and longer life-time of the system since the big bulk capacitors, usually implemented with OSCON capacitors, may not be needed to achieve the desired dynamic behavior. An additional advantage is that, by reducing the output capacitance, dynamic voltage scaling (DVS) can be performed faster and with smaller stress on the power stage, since the needed amount of charge to change the output voltage is smaller. The dynamic behavior of the system with a linear control (Voltage mode control, VMC, Peak Current Mode Control, PCMC,…) is limited by the converter switching frequency and filter size. The reduction of the output capacitor can be achieved by increasing the switching frequency of the converter, thus increasing the bandwidth of the system, and/or by applying advanced non-linear controls. Applying nonlinear control, the system variables get saturated in order to reach the new steady-state in a minimum time, thus the output filter, more specifically the output inductor current slew-rate, determines the output voltage response. Therefore, by reducing the output inductor value, the inductor current reaches faster the new steady state, so a smaller amount of charge is taken from the output capacitor during the transient. The drawback of this approach is that the system efficiency is penalized due to increased switching losses and RMS currents. In order to achieve both the output capacitor reduction and high system efficiency, while satisfying strict dynamic specifications, a Multiphase converter system is adopted as a standard for VRM applications. In order to ensure the current sharing among the phases, the multiphase converter is usually implemented with current mode control. In order to overcome the limitation imposed by the output filter, the second possibility to reduce the output capacitor is to apply Topologic modifications of the basic power stage topology in order to increase the slew-rate of the inductor current and, therefore, reduce the transient duration. Since the transient is reduced, smaller amount of charge is taken from the output capacitor under the same load current, thus, the output capacitor can be reduced to achieve the same output voltage deviation. The third possibility to reduce the output capacitor of the converter is to introduce an additional energy path (AEP) to compensate the charge unbalance of the output capacitor, consequently reducing the transient time and output voltage deviation. Doing so, during the steady-state operation the system has high efficiency because the main low-bandwidth converter is designed to operate at moderate switching frequency, to meet the static requirements, whereas the dynamic behavior during the transients is determined by the high-bandwidth auxiliary energy path. The auxiliary energy path can be implemented as a resistive path, as a Linear regulator, LR, or as a switching converter. The first two implementations provide higher bandwidth, at the expense of increasing losses during the transient. On the other hand, the switching converter implementation presents lower bandwidth, limited by the auxiliary converter switching frequency, though it produces smaller losses compared to the two previous implementations. Depending on the application, the implementation and the control strategy of the system, there is a variety of proposed solutions in the State-of-the-Art (SoA), having different features where one solution offers some advantages over the others, but also some disadvantages. In general, an ideal additional energy path system should have the following features: 1. The impact on the system losses should be minimal. During its operation, the AEP generates additional losses, thus ideally, the AEP should operate for a short period of time, only when the transient is occurring; the other option is to have the AEP constantly on, but due to the inductor current ripple compensation at the output, unnecessary losses are generated. 2. The AEP should be activated nearly instantaneously to prevent bigger output voltage deviation. To achieve near instantaneous activation, the converter system can be informed by the load prior to the load-step or the system can observe the output capacitor current, which is the first system state variable that reacts on the load current perturbation. In this manner, the AEP is turned on with near zero output voltage error, providing smaller output voltage deviation. 3. The AEP should be deactivated once the new steady state is reached to avoid additional settling transients. Most of the SoA solutions estimate duration of the transient which may cause additional transient if the estimation is not performed correctly (e.g. if the main converter inductor current has higher or lower value than needed, the slow regulator of the main converter needs to compensate the difference after the AEP is deactivated). Other SoA solutions are observing state variables, ensuring that the system reaches the new steady state or they are informed by the load. 4. During the transient, at least one subsystem, either the main converter or the AEP, should be in closed-loop. Implementing a closed loop system, preferably the AEP subsystem, due its higher bandwidth, increases the robustness under system tolerances and circuit parasitic. In addition, the AEP can operate with any type of load. The solutions that operate in open loop usually perform minimum time charge balance control, thus reducing the transient length and minimizing the impact on the losses, however they are very sensitive to tolerances and parasitics. 5. The AEP should inject current at the output in a controlled manner, thus reducing the risk of high and potentially damaging currents and increasing robustness on the input voltage deviation. This issue is mainly related to the systems where AEP is implemented as auxiliary converter. The auxiliary converter is designed for small power and, as such, the MOSFETs are rated for small power/currents. If the current is not controlled, due to the some unpredicted spike in input voltage caused by some other part of the system (e.g. different converter), it may lead to a current spike in auxiliary current which will cause the perturbation of the output voltage and even failure of the switching components of auxiliary converter. In the case when the current is controlled, using peak CMC or Hysteretic Window CMC, the auxiliary converter has inherent feed-forwarding of the input voltage in current control and the current is defined and limited. Furthermore, if the solution employs charge balance control, the system may perform poorly if the input voltage has different value than the nominal, causing that AEP injects/extracts more/less charge than needed. 6. Scalability of the system to multiphase converters. As commented previously, in VRM applications, due to the high load currents, the main converters are implemented as multiphase to redistribute losses among the modules, lowering temperature stress of the components. To ensure the current sharing, usually a Current Mode Control (CMC) is employed. The SoA solutions that are implemented with VMC are limited to a single stage implementation. This thesis proposes a novel control method of the energy flow through the AEP and the main converter system. The proposed concept relays on a controlled injection of the auxiliary current at the output node where the instantaneous current value is n-1 times bigger than the output capacitor current with appropriate directions. Doing so, the AEP creates an equivalent n times bigger virtual capacitor at the output, thus reducing the output impedance. Due to the fact that the proposed concept reduces the output impedance using the AEP, it has been named the Output Impedance Correction Circuit (OICC) concept. The concept is developed for a multiphase CMC synchronous buck converter (including a single phase implementation), operating with a constant output voltage and with AVP feature. Further, it is extended to a single phase VMC synchronous buck converter. During the operation, the main converter voltage loop and the OICC subsystem capacitor current loop is constantly closed, increasing the robustness under system tolerances and circuit parasitic and allowing the system to operate with any load-current shape or pattern. According to the proposed control method, the system operates in two states: during the steady-state the system is in the Idle state and the OICC subsystem is deactivated, while during the load-step transient the system is in the Active state and the OICC subsystem is activated in order to reduce the output impedance. The state changes are performed autonomously: the system enters in the Active state by observing the output capacitor current and it returns back to the Idle state when the steady-state operation is detected by observing the state variables. The validation of the OICC concept has been done by applying it to a 30W two phase synchronous buck converter with 140μF output capacitor and with the multiplication factor n equal to 15, generating during the Active state equivalent output capacitor of 2.1mF. The OICC subsystem is implemented as single phase PCMC synchronous buck converter. Comparing the converter operation with and without the OICC the results demonstrate that the 12 times reduction of the output voltage deviation is achieved, for both basic operation and for the AVP operation. Furthermore, the results have been compared to a reference prototype which has the same power stage and a fiscal output capacitor of 2.1mF. The results show that the two systems have the same dynamic behavior. Moreover, an impact on the system losses under the pulsating load and DVS operation has been quantified and it has been demonstrated that the OICC system has improved the system efficiency, considering the losses when the system operates with the pulsating load and the DVS operation. Lastly, the output capacitor of the OICC system is much smaller than the reference design output capacitor, therefore, by applying the OICC concept the power density can be increased. In summary, the main contributions of the thesis are: • The proposed Output Impedance Correction Circuit (OICC) concept, • The system level control based on the used approach to change the states of operation, • The OICC subsystem closed-loop implementation, together with the main converter implementation, • The dynamic losses under the pulsating load and the DVS operation quantification, and • The system robustness on the capacitor impedance variation and consecutive load-steps.

On multiple-path sonic anemometer measurement theory

In this paper, a model of the measuring process of sonic anemometers with more than one measuring path is presented. The main hypothesis of the work is that the time variation of the turbulent speed field during the sequence of pulses that produces a measure of the wind speed vector affects the measurement. Therefore, the previously considered frozen flow, or instantaneous averaging, condition is relaxed. This time variation, quantified by the mean Mach number of the flow and the time delay between consecutive pulses firings, in combination with both the full geometry of sensors (acoustic path location and orientation) and the incidence angles of the mean with speed vector, give rise to significant errors in the measurement of turbulence which are not considered by models based on the hypothesis of instantaneous line averaging. The additional corrections (relative to the ones proposed by instantaneous line-averaging models) are strongly dependent on the wave number component parallel to the mean wind speed, the time delay between consecutive pulses, the Mach number of the flow, the geometry of the sensor and the incidence angles of mean wind speed vector. Kaimal´s limit k W1=1/l (where k W1 is the wave number component parallel to mean wind speed and l is the path length) for the maximum wave numbers from which the sonic process affects the measurement of turbulence is here generalized as k W1=C l /l, where C l is usually lesser than unity and depends on all the new parameters taken into account by the present model.

Desynchronization of cells on the developmental path triggers the formation of spiral waves of cAMP during Dictyostelium aggregation

Whereas it is relatively easy to account for the formation of concentric (target) waves of cAMP in the course of Dictyostelium discoideum aggregation after starvation, the origin of spiral waves remains obscure. We investigate a physiologically plausible mechanism for the spontaneous formation of spiral waves of cAMP in D. discoideum. The scenario relies on the developmental path associated with the continuous changes in the activity of enzymes such as adenylate cyclase and phosphodiesterase observed during the hours that follow starvation. These changes bring the cells successively from a nonexcitable state to an excitable state in which they relay suprathreshold cAMP pulses, and then to autonomous oscillations of cAMP, before the system returns to an excitable state. By analyzing a model for cAMP signaling based on receptor desensitization, we show that the desynchronization of cells on this developmental path triggers the formation of fully developed spirals of cAMP. Developmental paths that do not correspond to the sequence of dynamic transitions no relay-relay-oscillations-relay are less able or fail to give rise to the formation of spirals.

Path-following analysis of the dynamical response of a piecewise-linear capsule system

Acknowledgements The first author has been supported by a Georg Forster Research Fellowship granted by the Alexander von Humboldt Foundation, Germany

Fatty acids and hypolipidemic drugs regulate peroxisome proliferator-activated receptors α- and γ-mediated gene expression via liver fatty acid binding protein: A signaling path to the nucleus

Peroxisome proliferator-activated receptor α (PPARα) is a key regulator of lipid homeostasis in hepatocytes and target for fatty acids and hypolipidemic drugs. How these signaling molecules reach the nuclear receptor is not known; however, similarities in ligand specificity suggest the liver fatty acid binding protein (L-FABP) as a possible candidate. In localization studies using laser-scanning microscopy, we show that L-FABP and PPARα colocalize in the nucleus of mouse primary hepatocytes. Furthermore, we demonstrate by pull-down assay and immunocoprecipitation that L-FABP interacts directly with PPARα. In a cell biological approach with the aid of a mammalian two-hybrid system, we provide evidence that L-FABP interacts with PPARα and PPARγ but not with PPARβ and retinoid X receptor-α by protein–protein contacts. In addition, we demonstrate that the observed interaction of both proteins is independent of ligand binding. Final and quantitative proof for L-FABP mediation was obtained in transactivation assays upon incubation of transiently and stably transfected HepG2 cells with saturated, monounsaturated, and polyunsaturated fatty acids as well as with hypolipidemic drugs. With all ligands applied, we observed strict correlation of PPARα and PPARγ transactivation with intracellular concentrations of L-FABP. This correlation constitutes a nucleus-directed signaling by fatty acids and hypolipidemic drugs where L-FABP acts as a cytosolic gateway for these PPARα and PPARγ agonists. Thus, L-FABP and the respective PPARs could serve as targets for nutrients and drugs to affect expression of PPAR-sensitive genes.

Least activation path for protein folding: investigation of staphylococcal nuclease folding by stopped-flow circular dichroism.

Is the pathway of protein folding determined by the relative stability of folding intermediates, or by the relative height of the activation barriers leading to these intermediates? This is a fundamental question for resolving the Levinthal paradox, which stated that protein folding by a random search mechanism would require a time too long to be plausible. To answer this question, we have studied the guanidinium chloride (GdmCl)-induced folding/unfolding of staphylococcal nuclease [(SNase, formerly EC 3.1.4.7; now called microbial nuclease or endonuclease, EC 3.1.31.1] by stopped-flow circular dichroism (CD) and differential scanning microcalorimetry (DSC). The data show that while the equilibrium transition is a quasi-two-state process, kinetics in the 2-ms to 500-s time range are triphasic. Data support the sequential mechanism for SNase folding: U3 <--> U2 <--> U1 <--> N0, where U1, U2, and U3 are substates of the unfolded protein and N0 is the native state. Analysis of the relative population of the U1, U2, and U3 species in 2.0 M GdmCl gives delta-G values for the U3 --> U2 reaction of +0.1 kcal/mol and for the U2 --> U1 reaction of -0.49 kcal/mol. The delta-G value for the U1 --> N0 reaction is calculated to be -4.5 kcal/mol from DSC data. The activation energy, enthalpy, and entropy for each kinetic step are also determined. These results allow us to make the following four conclusions. (i) Although the U1, U2, and U3 states are nearly isoenergetic, no random walk occurs among them during the folding. The pathway of folding is unique and sequential. In other words, the relative stability of the folding intermediates does not dictate the folding pathway. Instead, the folding is a descent toward the global free-energy minimum of the native state via the least activation path in the vast energy landscape. Barrier avoidance leads the way, and barrier height limits the rate. Thus, the Levinthal paradox is not applicable to the protein-folding problem. (ii) The main folding reaction (U1 --> N0), in which the peptide chain acquires most of its free energy (via van der Waals' contacts, hydrogen bonding, and electrostatic interactions), is a highly concerted process. These energy-acquiring events take place in a single kinetic phase. (iii) U1 appears to be a compact unfolded species; the rate of conversion of U2 to U1 depends on the viscosity of solution. (iv) All four relaxation times reported here depend on GdmCl concentrations: it is likely that none involve the cis/trans isomerization of prolines. Finally, a mechanism is presented in which formation of sheet-like chain conformations and a hydrophobic condensation event precede the main-chain folding reaction.

Codominance and toxins: a path to drugs of nearly unlimited selectivity.

The effectiveness of drugs is often limited by their insufficient selectivity. I propose designs of therapeutic agents that address this problem. The key feature of these reagents, termed comtoxins (codominance-mediated toxins), is their ability to utilize codominance, a property characteristic of many signals in proteins, including degradation signals (degrons) and nuclear localization signals. A comtoxin designed to kill cells that express intracellular proteins P1 and P2 but to spare cells that lack P1 and/or P2 is a multidomain fusion containing a cytotoxic domain and two degrons placed within or near two domains P1* and P2* that bind, respectively, to P1 and P2. In a cell containing both P1 and P2, these proteins would bind to the P1* and P2* domains of the comtoxin and sterically mask the nearby (appropriately positioned) degrons, resulting in a long-lived and therefore toxic drug. By contrast, in a cell lacking P1 and/or P2, at least one of the comtoxin's degrons would be active (unobstructed), yielding a short-lived and therefore nontoxic drug. A comtoxin containing both a degron and a nuclear localization signal can be designed to kill exclusively cells that contain P1 but lack P2. Analogous strategies yield comtoxins sensitive to the presence (or absence) of more than two proteins in a cell. Also considered is a class of comtoxins in which a toxic domain is split by a flexible insert containing binding sites for the target proteins. The potentially unlimited, combinatorial selectivity of comtoxins may help solve the problem of side effects that bedevils present-day therapies, for even nonselective delivery of a comtoxin would not affect cells whose protein "signatures" differ from the targeted one.

On Becoming a Working Visual Artist: Opportunities and Challenges Along the Path

Thousands of students graduate from colleges and art schools every year with the goal of becoming working visual artists. The majority of them, however, find that earning a living as a working artist is a tough and competitive career path. This Capstone Project, through an extensive literature review and interviews, examines the factors and characteristics that influence whether an individual will make the leap to becoming a working visual artist. Research results indicate that primary factors in achieving the status of working visual artists include specific personality traits, experiential and career-oriented arts education, and development of strong business skills.

Efficient tool path computation using multi-core GPUs

Tool path generation is one of the most complex problems in Computer Aided Manufacturing. Although some efficient strategies have been developed, most of them are only useful for standard machining. However, the algorithms used for tool path computation demand a higher computation performance, which makes the implementation on many existing systems very slow or even impractical. Hardware acceleration is an incremental solution that can be cleanly added to these systems while keeping everything else intact. It is completely transparent to the user. The cost is much lower and the development time is much shorter than replacing the computers by faster ones. This paper presents an optimisation that uses a specific graphic hardware approach using the power of multi-core Graphic Processing Units (GPUs) in order to improve the tool path computation. This improvement is applied on a highly accurate and robust tool path generation algorithm. The paper presents, as a case of study, a fully implemented algorithm used for turning lathe machining of shoe lasts. A comparative study will show the gain achieved in terms of total computing time. The execution time is almost two orders of magnitude faster than modern PCs.

Teaching-learning process of historical heritage: a Journey as a beginning, path and end

The implantation of new university degrees within the European Higher Education Area implies the need of innovative methodologies in teaching and learning to improve the skills and competencies of students and to answer the growing needs that society continuously demands to heritage management experts. The present work shows an application of the teaching methodology proposed during the international workshop entitled “I International Planning Preservation Workshop. Learning from Al Andalus”, which included the participation of the University of Alicante and Granada, Università Politecnico di Milano and Hunter College City University of New York; where we tried to dissolve traditional boundaries derived of interuniversity cooperation programs. The main objective of the workshop was to discuss and debate the role of urban Historical Centers within the Global Heritage by the integrated work through multidisciplinary teams and the creation of a permanent international working group between these universities to both teach and research. The methodology of this workshop was very participatory and considered the idea of a new learning process generated by "a journey experience." A trip from global to local (from the big city to the small village) but also a trip from the local (historical) part of a big city to the global dimension of contemporary historical villages identified by the students through a system of exhibition panels in affinity groups, specific projects proposed by lecturers and teachers or the generation of publications in various areas (texts, photographs, videos, etc.). So, the participation of the students in this multidisciplinary meeting has enhanced their capacity for self-criticism in several disciplines and has promoted their ability to perform learning and research strategies in an autonomous way. As a result, it has been established a permanent international work structure for the development of projects of the Historical City. This relationship has generated the publication of several books whose contents have reflected the conclusions developed in the workshop and several teaching proposals shared between those institutions. All these aspects have generated a new way of understanding the teaching process through a journey, in order to study the representative role of university in the historical heritage and to make students (from planning, heritage management, architecture, geography, sociology, history or engineering areas) be compromised on searching strategies for sustainable development in the Contemporary City.