House value as an indicator of cumulative wealth is strongly related to morbidity and mortality risk in older people: a census-based cross-sectional and longitudinal study

Background: There has been relatively little research into health inequalities in older populations. This may be partly explained by the difficulty in identifying appropriate indicators of socio-economic status for older people. Ideally, indicators of socio-economic status to be used in studies of health inequalities in older populations should incorporate some measure of life-time socio-economic standing, and house value may fill this role. This study examined whether an indicator of accumulated wealth based on a combination of housing tenure and house value was a strong predictor of ill-health in older populations.
Methods: A total of 191 848 people aged =65 years and not living in communal establishments were identified from the 2001 Northern Ireland Census and followed for 5 years. Self-reported health and mortality risk by housing tenure/house value groupings were examined while controlling for a range of other demographic and socio-economic characteristics.
Results: Housing tenure/house value was highly correlated with other indicators of socio-economic status. Public-sector renters had worse self-reported health and higher mortality rates than owner occupiers but significant gradients were also found between those living in the highest-and lowest-valued owner-occupier properties. The relationship between housing tenure and value was unchanged by adjustment for indicators of social support and quality of the physical environment. Adjustment for limiting long-term illness and self-reported health at baseline narrowed but did not eliminate the health gains associated with living in more expensive housing.
Conclusions: House value of residence is an accessible and powerful indicator of accumulated wealth that is highly correlated with current health status and predictive of future mortality risk in older populations.

Information gathering and decision making about resource value in animal contests

Contestants are predicted to adjust the cost of a fight in line with the perceived value of the resource and this provides a way of determining whether the resource has been assessed. An assessment of resource value is predicted to alter an animal's motivational state and we note different methods of measuring that state. We provide a categorical framework in which the degree of resource assessment may be evaluated and also note limitations of various approaches. We place studies in six categories: (1) cases of no assessment, (2) cases of internal state such as hunger influencing apparent value, (3) cases of the contestants differing in assessment ability, (4) cases of mutual and equal assessment of value, (5) cases where opponents differ in resource value and (6) cases of particularly complex assessment abilities that involve a comparison of the value of two resources. We examine the extent to which these studies support game theory predictions and suggest future areas of research. (C) 2008 The Association for the Study of Animal Behaviour. Published by Elsevier Ltd. All rights reserved.

Vanity Fair; The Clangers; The Reversal

Three poems.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.