A clocking technique for FPGA pipelined designs

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. (C) 2004 Elsevier B.V. All rights reserved.

A block coprocessor for user data rate improvements to GPRS coding scheme 4

The general packet radio service (GPRS) has been developed to allow packet data to be transported efficiently over an existing circuit-switched radio network, such as GSM. The main application of GPRS are in transporting Internet protocol (IP) datagrams from web servers (for telemetry or for mobile Internet browsers). Four GPRS baseband coding schemes are defined to offer a trade-off in requested data rates versus propagation channel conditions. However, data rates in the order of > 100 kbits/s are only achievable if the simplest coding scheme is used (CS-4) which offers little error detection and correction (EDC) (requiring excellent SNR) and the receiver hardware is capable of full duplex which is not currently available in the consumer market. A simple EDC scheme to improve the GPRS block error rate (BLER) performance is presented, particularly for CS-4, however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel and improving the user's application data rate. As GPRS requires intensive processing in the baseband, a viable field programmable gate array (FPGA) solution is presented in this paper.

A novel radix-3/9 algorithm for type-III generalized discrete Hartley transform

A novel radix-3/9 algorithm for type-III generalized discrete Hartley transform (GDHT) is proposed, which applies to length-3(P) sequences. This algorithm is especially efficient in the case that multiplication is much more time-consuming than addition. A comparison analysis shows that the proposed algorithm outperforms a known algorithm when one multiplication is more time-consuming than five additions. When combined with any known radix-2 type-III GDHT algorithm, the new algorithm also applies to length-2(q)3(P) sequences.

Identification and minimization of IIR tap coefficients for the cancellation of complex multipath in terrestrial television

By using a deterministic approach, an exact form for the synchronous detected video signal under a ghosted condition is presented. Information regarding the phase quadrature-induced ghost component derived from the quadrature forming nature of the vestigial sideband (VSB) filter is obtained by crosscorrelating the detected video with the ghost cancel reference (GCR) signal. As a result, the minimum number of taps required to correctly remove all the ghost components is subsequently presented. The results are applied to both National Television System Committee (NTSC) and phase alternate line (PAL) television.

Improving mW/MHz ratio in FPGAs pipelined designs

This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.

Pipelining considerations for an FPGA case

This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.

Suppression of directional interference for STBC MIMO system based on beam-forming

In civil applications, many researches on MIMO technique have achieved great progress. However, we consider military applications here. Differing from civil applications, military MIMO system may face many kinds of interferences, and the interference source may even not be equipped with multiple antennas. So the military MIMO system may receive some kind of strong interference coming from certain direction. Therefore, the military MIMO system must have capability to suppress directional interference. This paper presents a scheme to suppress directional interference for STBC MIMO system based on beam-forming. Simulation result shows that the scheme is valid to suppress directional strong interference for STBC MIMO system although with some performance loss compared with the ideal case of non-interference.

Improved process topology for membrane distillation

In membrane distillation in a conventional membrane module, the enthalpies of vaporisation and condensation are supplied and removed by changes in the temperatures of the feed and permeate streams, respectively. Less than 5% of the feed can be distilled in a single pass, because the potential changes in the enthalpies of the liquid streams are much smaller than the enthalpy of vaporisation. Furthermore, the driving force for mass transfer reduces as the feed stream temperature and vapour pressure fall during distillation. These restrictions can be avoided if the enthalpy of vaporisation is uncoupled from the heat capacities of the feed and permeate streams. A specified distillation can then be effected continuously in a single module. Calculations are presented which estimate the performance of a flat plate unit in which the enthalpy of distillation is supplied and removed by the condensing and boiling of thermal fluids in separate circuits, and the imposed temperature difference is independent of position. Because the mass flux through the membrane is dependent on vapour pressure, membrane distillation is suited to applications with a high membrane temperature. The maximum mass flux in the proposed module geometry is predicted to be 30 kg/m2 per h at atmospheric pressure when the membrane temperature is 65°C. Operation at higher membrane temperatures is predicted to raise the mass flux, for example to 85 kg/m2 per h at a membrane temperature of 100°C. This would require pressurisation to 20 bar to prevent boiling at the heating plate of the feed channel. Pre-pressurisation of the membrane pores and control of the dissolved gas concentrations in the feed and the recyled permeate should be investigated as a means to achieve high temperature membrane distillation without pore penetration and wetting.

Communication mechanisms and middleware for distributed video surveillance

A new generation of advanced surveillance systems is being conceived as a collection of multi-sensor components such as video, audio and mobile robots interacting in a cooperating manner to enhance situation awareness capabilities to assist surveillance personnel. The prominent issues that these systems face are: the improvement of existing intelligent video surveillance systems, the inclusion of wireless networks, the use of low power sensors, the design architecture, the communication between different components, the fusion of data emerging from different type of sensors, the location of personnel (providers and consumers) and the scalability of the system. This paper focuses on the aspects pertaining to real-time distributed architecture and scalability. For example, to meet real-time requirements, these systems need to process data streams in concurrent environments, designed by taking into account scheduling and synchronisation. The paper proposes a framework for the design of visual surveillance systems based on components derived from the principles of Real Time Networks/Data Oriented Requirements Implementation Scheme (RTN/DORIS). It also proposes the implementation of these components using the well-known middleware technology Common Object Request Broker Architecture (CORBA). Results using this architecture for video surveillance are presented through an implemented prototype.

Duality, observability, and controllability for linear time-varying descriptor systems

A characterization of observability for linear time-varying descriptor systemsE(t)x(t)+F(t)x(t)=B(t)u(t), y(t)=C(t)x(t) was recently developed. NeitherE norC were required to have constant rank. This paper defines a dual system, and a type of controllability so that observability of the original system is equivalent to controllability of the dual system. Criteria for observability and controllability are given in terms of arrays of derivatives of the original coefficients. In addition, the duality results of this paper lead to an improvement on a previous fundamental structure result for solvable systems of the formE(t)x(t)+F(t)x(t)=f(tt).

Implementation of Parallel (p,q) Counters for High Speed Digital Multipliers

Both the (5,3) counter and (2,2,3) counter multiplication techniques are investigated for the efficiency of their operation speed and the viability of the architectures when implemented in a fast bipolar ECL technology. The implementation of the counters in series-gated ECL and threshold logic are contrasted for speed, noise immunity and complexity, and are critically compared with the fastest practical design of a full-adder. A novel circuit technique to overcome the problems of needing high fan-in input weights in threshold circuits through the use of negative weighted inputs is presented. The authors conclude that a (2,2,3) counter based array multiplier implemented in series-gated ECL should enable a significant increase in speed over conventional full adder based array multipliers.

Parallel Architectures for High Speed Multipliers

The authors compare various array multiplier architectures based on (p,q) counter circuits. The tradeoff in multiplier design is always between adding complexity and increasing speed. It is shown that by using a (2,2,3) counter cell it is possible to gain a significant increase in speed over a conventional full-adder, carry-save array based approach. The increase in complexity should be easily accommodated using modern emitter-coupled-logic processes.

Digital predistorter design using B-Spline neural network and inverse of De Boor algorithm

This contribution introduces a new digital predistorter to compensate serious distortions caused by memory high power amplifiers (HPAs) which exhibit output saturation characteristics. The proposed design is based on direct learning using a data-driven B-spline Wiener system modeling approach. The nonlinear HPA with memory is first identified based on the B-spline neural network model using the Gauss-Newton algorithm, which incorporates the efficient De Boor algorithm with both B-spline curve and first derivative recursions. The estimated Wiener HPA model is then used to design the Hammerstein predistorter. In particular, the inverse of the amplitude distortion of the HPA's static nonlinearity can be calculated effectively using the Newton-Raphson formula based on the inverse of De Boor algorithm. A major advantage of this approach is that both the Wiener HPA identification and the Hammerstein predistorter inverse can be achieved very efficiently and accurately. Simulation results obtained are presented to demonstrate the effectiveness of this novel digital predistorter design.

The Prophetic Sound: a day and night of noise cabaret(symposium of talks and live performances)

'The Prophetic Sound: a day and night of noise cabaret' is the first event hosted by Agency of Noise. This all day event brought together artists and academics whose subject of focus is noise (in creative practice). Artists from across the UK were invited to consider a future post-digital era in which everything with a microchip has malfunctioned, as a thought exercise and starting point for response through sound. In response to Jacques Attali’s claim that music is prophecy, The Prophetic Sound asks us to consider if noise can communicate in an unbridled, unfiltered, way that is somehow not culturally coded -before it becomes sound that is recognised, refined, manipulated and exploited for musical or other cultured purpose. Featuring students from Reading, Brighton, LCC and Goldsmiths alongside more established artists and academics from across the UK, this event brings into focus locations where pattern, timbre, pitch, organisation and sequencing of sounds become distinguishable from noise and asks us to consider, through diversion within such locations, new origins for future communication systems. The Prophetic Sound included talks, films, presentations and performances from: Ryo Ikeshiro / Inigo Wilkins / Neal Spowage / Dane Sutherland / Poulomi Desai / Benedict Drew / AAS / Polly Fibre / Steven Dickie As part of The Prophetic Sound, POLLYFIBRE (Ellison, C.) performed LIVE RECORDING with Amplified Scissors. This industrial activity by POLLYFIBRE short-circuits the complicated chain that is music production. The distinctive roles of consumer, producer, composer, and performer collapse in a series of live ‘cuts’ where vinyl discs are produced with amplified scissors. Production happens through action and action becomes production. A limited edition of 9 flexi discs were produced and available for special collectors at the event.

Fractional order modeling of large three-dimensional RC networks

An incidence matrix analysis is used to model a three-dimensional network consisting of resistive and capacitive elements distributed across several interconnected layers. A systematic methodology for deriving a descriptor representation of the network with random allocation of the resistors and capacitors is proposed. Using a transformation of the descriptor representation into standard state-space form, amplitude and phase admittance responses of three-dimensional random RC networks are obtained. Such networks display an emergent behavior with a characteristic Jonscher-like response over a wide range of frequencies. A model approximation study of these networks is performed to infer the admittance response using integral and fractional order models. It was found that a fractional order model with only seven parameters can accurately describe the responses of networks composed of more than 70 nodes and 200 branches with 100 resistors and 100 capacitors. The proposed analysis can be used to model charge migration in amorphous materials, which may be associated to specific macroscopic or microscopic scale fractal geometrical structures in composites displaying a viscoelastic electromechanical response, as well as to model the collective responses of processes governed by random events described using statistical mechanics.