927 resultados para graphics processor


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Pattern recognition in large amount of data has been paramount in the last decade, since that is not straightforward to design interactive and real time classification systems. Very recently, the Optimum-Path Forest classifier was proposed to overcome such limitations, together with its training set pruning algorithm, which requires a parameter that has been empirically set up to date. In this paper, we propose a Harmony Search-based algorithm that can find near optimal values for that. The experimental results have showed that our algorithm is able to find proper values for the OPF pruning algorithm parameter. © 2011 IEEE.

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This work describes a hardware/software co-design system development, named IEEE 1451 platform, to be used in process automation. This platform intends to make easier the implementation of IEEE standards 1451.0, 1451.1, 1451.2 and 1451.5. The hardware was built using NIOS II processor resources on Alteras Cyclone II FPGA. The software was done using Java technology and C/C++ for the processors programming. This HW/SW system implements the IEEE 1451 based on a control module and supervisory software for industrial automation. © 2011 Elsevier B.V.

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This paper presents a network node embedded based on IEEE 1451 standard developed using structured programming to access the transducers in the WTIM. The NCAP was developed using Nios II processor and uClinux, a embedded operating system developed to features restricted hardware. Both hardware and software have dynamics features and they can be configured based in the application features. Based in this features, the NCAP was developed using the minimum components of hardware and software to that being implemented in remote environment like central point of data request. Many NCAP works are implemented with an object oriented structure. This is different from the surrounding implementations. In this project the NCAP was developed using structured programming. The tests of the NCAP were made using a ZigBee interface between NCAP and WTIM and the system demonstrated in areas of difficult access for long period of time due to need for low power consumption. © 2012 IEEE.

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Tests on spatial aptitude, in particular Visualization, have been shown to be efficient predictors of the academic performance of Technical Drawing stu-dents. It has recently been found that Spatial Working Memory (a construct defined as the ability to perform tasks with a figurative content that require si-multaneous storage and transformation of information) is strongly associated with Visualization. In the present study we analyze the predictive efficiency of a bat-tery of tests that included tests on Visualization, SpatialWorking Memory, Spatial Short-term Memory and Executive Function on a sample of first year engineering students. The results show that Spatial Working Memory (SWM) is the most important predictor of academic success in Technical Drawing. In our view, SWM tests can be useful for detecting as early as possible those students who will require more attention and support in the teaching-learning process.

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Digital data sets constitute rich sources of information, which can be extracted and evaluated applying computational tools, for example, those ones for Information Visualization. Web-based applications, such as social network environments, forums and virtual environments for Distance Learning, are good examples for such sources. The great amount of data has direct impact on processing and analysis tasks. This paper presents the computational tool Mapper, defined and implemented to use visual representations - maps, graphics and diagrams - for supporting the decision making process by analyzing data stored in Virtual Learning Environment TelEduc-Unesp. © 2012 IEEE.

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Multipulse rectifiers can replace a conventional six pulse three-phase rectifier (diode bridge) providing a DC voltage with low ripple, low Total Harmonic Distortion of current (THDi) and a high Power Factor (PF). In this context is presented a multipulse rectifier with generalized Delta-differential autotransformer topology, which can provide any level of DC output voltage for any level of three-phase AC input voltage. This paper presents all the possible configurations for Delta topology in order to choose, through graphics, one configuration that presents reduced weight and volume. The average voltage on the DC bus must be compatible with the DC voltage in the six pulse rectifier used in commercial ASDs. Therefore, it is possible to apply the retrofit technique to replace the conventional bridge rectifier by the proposed multipulse rectifier. Based on mathematic models and simulation results, an 18-pulse rectifier with Delta topology, 220 V of line voltage, 315 V of DC output, and rating 2.5 kW of power was designed, implemented and applied for three different commercial ASDs. Experimental results as voltage and current waveforms and results about PF and THDi will be presented. © 2012 IEEE.

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Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of TM (STM) have been extensively analyzed in terms of runtime performance, little attention has been paid to an equally important constraint faced by nearly all computer systems: energy consumption. In this work we conduct a comprehensive study of energy and runtime tradeoff sin software transactional memory systems. We characterize the behavior of three state-of-the-art lock-based STM algorithms, along with three different conflict resolution schemes. As a result of this characterization, we propose a DVFS-based technique that can be integrated into the resolution policies so as to improve the energy-delay product (EDP). Experimental results show that our DVFS-enhanced policies are indeed beneficial for applications with high contention levels. Improvements of up to 59% in EDP can be observed in this scenario, with an average EDP reduction of 16% across the STAMP workloads. © 2012 IEEE.

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The implementation of vibration analysis techniques based on virtual instrumentation has spread increasingly in the academic and industrial branch, since the use of any software for this type of analysis brings good results at low cost. Among the existing software for programming and creation of virtual instruments, the LabVIEW was chosen for this project. This software has good interface with the method of graphical programming. In this project, it was developed a system of rotating machine condition monitoring. This monitoring system is applied in a test stand, simulating large scale applications, such as in hydroelectric, nuclear and oil exploration companies. It was initially used a test stand, where an instrumentation for data acquisition was inserted, composed of accelerometers and inductive proximity sensors. The data collection system was structured on the basis of an NI 6008 A/D converter of National Instruments. An electronic circuit command was developed through the A/D converter for a remote firing of the test stand. The equipment monitoring is performed through the data collected from the sensors. The vibration signals collected by accelerometers are processed in the time domain and frequency. Also, proximity probes were used for the axis orbit evaluation and an inductive sensor for the rotation and trigger measurement. © (2013) Trans Tech Publications, Switzerland.

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Software transaction memory (STM) systems have been used as an approach to improve performance, by allowing the concurrent execution of atomic blocks. However, under high-contention workloads, STM-based systems can considerably degrade performance, as transaction conflict rate increases. Contention management policies have been used as a way to select which transaction to abort when a conflict occurs. In general, contention managers are not capable of avoiding conflicts, as they can only select which transaction to abort and the moment it should restart. Since contention managers act only after a conflict is detected, it becomes harder to effectively increase transaction throughput. More proactive approaches have emerged, aiming at predicting when a transaction is likely to abort, postponing its execution. Nevertheless, most of the proposed proactive techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction to run. This article proposes LUTS, a lightweight user-level transaction scheduler. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. We discuss LUTS design and propose a dynamic conflict-avoidance heuristic built around its scheduling capabilities. Experimental results, conducted with the STAMP and STMBench7 benchmark suites, running on TinySTM and SwissTM, show how our conflict-avoidance heuristic can effectively improve STM performance on high contention applications. © 2012 Springer Science+Business Media, LLC.

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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

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Pós-graduação em Estudos Linguísticos - IBILCE

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Pós-graduação em Artes - IA

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)