Statistical models for short-term wind power ramp forecasting

La predicción de energía eólica ha desempeñado en la última década un papel fundamental en el aprovechamiento de este recurso renovable, ya que permite reducir el impacto que tiene la naturaleza fluctuante del viento en la actividad de diversos agentes implicados en su integración, tales como el operador del sistema o los agentes del mercado eléctrico. Los altos niveles de penetración eólica alcanzados recientemente por algunos países han puesto de manifiesto la necesidad de mejorar las predicciones durante eventos en los que se experimenta una variación importante de la potencia generada por un parque o un conjunto de ellos en un tiempo relativamente corto (del orden de unas pocas horas). Estos eventos, conocidos como rampas, no tienen una única causa, ya que pueden estar motivados por procesos meteorológicos que se dan en muy diferentes escalas espacio-temporales, desde el paso de grandes frentes en la macroescala a procesos convectivos locales como tormentas. Además, el propio proceso de conversión del viento en energía eléctrica juega un papel relevante en la ocurrencia de rampas debido, entre otros factores, a la relación no lineal que impone la curva de potencia del aerogenerador, la desalineación de la máquina con respecto al viento y la interacción aerodinámica entre aerogeneradores. En este trabajo se aborda la aplicación de modelos estadísticos a la predicción de rampas a muy corto plazo. Además, se investiga la relación de este tipo de eventos con procesos atmosféricos en la macroescala. Los modelos se emplean para generar predicciones de punto a partir del modelado estocástico de una serie temporal de potencia generada por un parque eólico. Los horizontes de predicción considerados van de una a seis horas. Como primer paso, se ha elaborado una metodología para caracterizar rampas en series temporales. La denominada función-rampa está basada en la transformada wavelet y proporciona un índice en cada paso temporal. Este índice caracteriza la intensidad de rampa en base a los gradientes de potencia experimentados en un rango determinado de escalas temporales. Se han implementado tres tipos de modelos predictivos de cara a evaluar el papel que juega la complejidad de un modelo en su desempeño: modelos lineales autorregresivos (AR), modelos de coeficientes variables (VCMs) y modelos basado en redes neuronales (ANNs). Los modelos se han entrenado en base a la minimización del error cuadrático medio y la configuración de cada uno de ellos se ha determinado mediante validación cruzada. De cara a analizar la contribución del estado macroescalar de la atmósfera en la predicción de rampas, se ha propuesto una metodología que permite extraer, a partir de las salidas de modelos meteorológicos, información relevante para explicar la ocurrencia de estos eventos. La metodología se basa en el análisis de componentes principales (PCA) para la síntesis de la datos de la atmósfera y en el uso de la información mutua (MI) para estimar la dependencia no lineal entre dos señales. Esta metodología se ha aplicado a datos de reanálisis generados con un modelo de circulación general (GCM) de cara a generar variables exógenas que posteriormente se han introducido en los modelos predictivos. Los casos de estudio considerados corresponden a dos parques eólicos ubicados en España. Los resultados muestran que el modelado de la serie de potencias permitió una mejora notable con respecto al modelo predictivo de referencia (la persistencia) y que al añadir información de la macroescala se obtuvieron mejoras adicionales del mismo orden. Estas mejoras resultaron mayores para el caso de rampas de bajada. Los resultados también indican distintos grados de conexión entre la macroescala y la ocurrencia de rampas en los dos parques considerados. Abstract One of the main drawbacks of wind energy is that it exhibits intermittent generation greatly depending on environmental conditions. Wind power forecasting has proven to be an effective tool for facilitating wind power integration from both the technical and the economical perspective. Indeed, system operators and energy traders benefit from the use of forecasting techniques, because the reduction of the inherent uncertainty of wind power allows them the adoption of optimal decisions. Wind power integration imposes new challenges as higher wind penetration levels are attained. Wind power ramp forecasting is an example of such a recent topic of interest. The term ramp makes reference to a large and rapid variation (1-4 hours) observed in the wind power output of a wind farm or portfolio. Ramp events can be motivated by a broad number of meteorological processes that occur at different time/spatial scales, from the passage of large-scale frontal systems to local processes such as thunderstorms and thermally-driven flows. Ramp events may also be conditioned by features related to the wind-to-power conversion process, such as yaw misalignment, the wind turbine shut-down and the aerodynamic interaction between wind turbines of a wind farm (wake effect). This work is devoted to wind power ramp forecasting, with special focus on the connection between the global scale and ramp events observed at the wind farm level. The framework of this study is the point-forecasting approach. Time series based models were implemented for very short-term prediction, this being characterised by prediction horizons up to six hours ahead. As a first step, a methodology to characterise ramps within a wind power time series was proposed. The so-called ramp function is based on the wavelet transform and it provides a continuous index related to the ramp intensity at each time step. The underlying idea is that ramps are characterised by high power output gradients evaluated under different time scales. A number of state-of-the-art time series based models were considered, namely linear autoregressive (AR) models, varying-coefficient models (VCMs) and artificial neural networks (ANNs). This allowed us to gain insights into how the complexity of the model contributes to the accuracy of the wind power time series modelling. The models were trained in base of a mean squared error criterion and the final set-up of each model was determined through cross-validation techniques. In order to investigate the contribution of the global scale into wind power ramp forecasting, a methodological proposal to identify features in atmospheric raw data that are relevant for explaining wind power ramp events was presented. The proposed methodology is based on two techniques: principal component analysis (PCA) for atmospheric data compression and mutual information (MI) for assessing non-linear dependence between variables. The methodology was applied to reanalysis data generated with a general circulation model (GCM). This allowed for the elaboration of explanatory variables meaningful for ramp forecasting that were utilized as exogenous variables by the forecasting models. The study covered two wind farms located in Spain. All the models outperformed the reference model (the persistence) during both ramp and non-ramp situations. Adding atmospheric information had a noticeable impact on the forecasting performance, specially during ramp-down events. Results also suggested different levels of connection between the ramp occurrence at the wind farm level and the global scale.

Documentación de estudio para sistemas audiovisuales

Este proyecto es una documentación sintetizada, para los alumnos de Grado en Imagen y Sonido, de todos los conceptos que conciernen a la asignatura Sistemas Audiovisuales. No obstante puede servir para todo aquel al que le interese la materia, sin ser necesariamente estudiante. El material se basa en la recopilación de libros de diversos autores, páginas web y catálogos de productos de empresas del sector audiovisual. Se intenta con esto incentivar en el auto-aprendizaje, proporcionando multitud de fuentes de información. El documento se ha dividido en dos bloques temáticos correspondientes a los temas: 1- Dispositivos de captación y reproducción de sonido e imagen. 2- Señales y formatos de audio y vídeo. Aunque no es tema de este proyecto pero si de la asignatura hay que nombrar el tercer bloque temático, Introducción a los sistemas de transmisión de audio y vídeo. Dado que hay suficiente documentación de estudio sobre éste se ha optado por no incluirlo. Cada bloque temático a su vez contiene cuatro unidades didácticas. Cada unidad se ha desarrollado de manera independiente a las demás, es decir, que cada unidad puede ser estudiada sin necesidad de recurrir a otras unidades para comprender la/s que interesa/n. Por otro lado hay que remarcar que todos los capítulos tienen relación entre sí. La documentación se complementa al final de cada unidad didáctica con un test de evaluación que a su vez ha sido publicado dentro del entorno de Moodle en la página correspondiente a la asignatura. Para ello se ha accedido a esta plataforma on line con el rol de editor de contenido. Para la elaboración de los cuestionarios se han tomado los conceptos clave de cada unidad didáctica, de esta manera los alumnos pueden saber si han comprendido lo que se explica en la documentación y mejorar así sus conocimientos. Para la redacción y estructuración de cada unidad didáctica, así como el documento en general, se ha cogido como referencia la Taxonomía de objetivos de la Educación o Taxonomía de Bloom. Dado que el dominio cognitivo del lector se encuadra dentro del ‘nivel de comprensión’, el documento no resulta tedioso en su estudio. No obstante introduce al alumno en los temas más importantes de la materia, proporcionando una base sólida de conocimiento en sistemas audiovisuales. Es precisamente el interés en hacer lo más accesible posible este documento lo que ha dificultado su elaboración, ya que el área de estudio es muy extensa y es difícil sintetizar sin eliminar contenido importante. No obstante para hacer más fiable el documento se ha seguido las pautas temáticas y argumentales marcadas por el Departamento Ingeniería Audiovisual y Comunicaciones de la Escuela Universitaria de Ingeniería Técnica de Telecomunicaciones de la Universidad Politécnica de Madrid verificando cada uno de los capítulos con los profesores de este departamento. Al tratarse de un proyecto con fines académicos, el texto se ha apoyado por figuras, esquemas, tablas, anexos y desarrollo de ecuaciones para hacer más comprensible lo que se expone. Algunos de estas informaciones se incluyen en inglés y no se ha creído conveniente su traducción dado que gran parte de la información que encontrará el alumno a lo largo de la carrera vendrá escrita en este idioma. Por último hay que decir al lector que es conveniente, pero no necesario, tener ciertas nociones de cálculo, álgebra, ondas y circuitos para seguir con fluidez lo que a continuación se expone. ABSTRACT. This project concerns all the concepts and topics of the subject Audiovisual Systems. It has been created for students of Sound and Image Degree, however everyone who's interested in this subject could use it even if isn’t a student. The document is divided into two main thematic sections corresponding to the topics: 1- Catchment and reproduction devices of sound and image. 2- Audio and video signals and formats. Even if this subject it isn’t mention in this project, it’s very important to quote a third important thematic of this block , such as Introduction about Transmission of Audio and Video System. Since there is enough study-documentation about this topic, it has been taken the choice to don’t integrate this chapter in this project. Every thematic block in this project is divided in chapters that have been developed in an independent way: that’s means that for each unit it is not necessary to look forward to other chapters in this project On the other hand it is necessary to emphasize that all the chapters are related one to each other. Every didactic unit and chapter ends with an evaluation test , that has been published with Moodle System using a content editor account. Those exercises will help in a easy way the student to improve his skills and his own ability. Collection of books of various authors, websites and product catalogs of audiovisual companies are used in this document and are included for stimulate the curiosity of the student. The key concepts of each unit have been used for making tests, so in this way students could be able to know if they have understood what the documentation explains and improve his skills. For writing and building each didactic unit, such as in the general document, it has been taken reference from Bloom’s Taxonomy. Since the skills and competence of the student are concentrated in the ‘comprehension level’, it will not be very complicated or hard to study. In spite of everything, all of thematic treated and discussed in documentation gives a solid knowledge of topic about audiovisual systems. The most difficult thing of realizing this document it was to take very complex topic and try to explain them as simply as possible In spite of everything for making this document as much accurated as possible it has been taken as point of reference rules established by the Department of Audiovisual Engineering & Communications of University School of Telecommunications Engineering (EUITT-UPM). This Project reach academic goal, for this reason in this document images, tables, annexes and outlines are enclosed in this document for an easier compression. At last, it’s necessary to say that each lector must have necessary a basic knowledge about arithmetic, calculus, waves and electronic circuits in the order that he could follow in a fluently way what the documentation set out.

Lineability of the set of holomorphic mappings with dense range

Let U be an open subset of a separable Banach space. Let F be the collection of all holomorphic mappings f from the open unit disc D � C into U such that f(D) is dense in U. We prove the lineability and density of F in appropriate spaces for diferent choices of U. RESUMEN. Sea U un subconjunto abierto de un espacio de Banach separable. Sea F el conjunto de funciones holomorfas f definidas en el disco unidad D del plano complejo con valores en U tales que f(D) es denso en U. En el artículo se demuestra la lineabilidad y densidad del conjunto F para diferentes elecciones de U.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Image analysis by moment invariants using a set of step-like basis functions

Moment invariants have been thoroughly studied and repeatedly proposed as one of the most powerful tools for 2D shape identification. In this paper a set of such descriptors is proposed, being the basis functions discontinuous in a finite number of points. The goal of using discontinuous functions is to avoid the Gibbs phenomenon, and therefore to yield a better approximation capability for discontinuous signals, as images. Moreover, the proposed set of moments allows the definition of rotation invariants, being this the other main design concern. Translation and scale invariance are achieved by means of standard image normalization. Tests are conducted to evaluate the behavior of these descriptors in noisy environments, where images are corrupted with Gaussian noise up to different SNR values. Results are compared to those obtained using Zernike moments, showing that the proposed descriptor has the same performance in image retrieval tasks in noisy environments, but demanding much less computational power for every stage in the query chain.

Set agreement and the loneliness failure detector in crash-recovery systems

The set agreement problem states that from n proposed values at most n-1 can be decided. Traditionally, this problem is solved using a failure detector in asynchronous systems where processes may crash but not recover, where processes have different identities, and where all processes initially know the membership. In this paper we study the set agreement problem and the weakest failure detector L used to solve it in asynchronous message passing systems where processes may crash and recover, with homonyms (i.e., processes may have equal identities) and without a complete initial knowledge of the membership.

High temperature micropillar compression of Al/SiC nanolaminates

The effect of the temperature on the compressive stress–strain behavior of Al/SiC nanoscale multilayers was studied by means of micropillar compression tests at 23 °C and 100 °C. The multilayers (composed of alternating layers of 60 nm in thickness of nanocrystalline Al and amorphous SiC) showed a very large hardening rate at 23 °C, which led to a flow stress of 3.1 ± 0.2 GPa at 8% strain. However, the flow stress (and the hardening rate) was reduced by 50% at 100 °C. Plastic deformation of the Al layers was the dominant deformation mechanism at both temperatures, but the Al layers were extruded out of the micropillar at 100 °C, while Al plastic flow was constrained by the SiC elastic layers at 23 °C. Finite element simulations of the micropillar compression test indicated the role played by different factors (flow stress of Al, interface strength and friction coefficient) on the mechanical behavior and were able to rationalize the differences in the stress–strain curves between 23 °C and 100 °C.

Determination of the hoop fracture properties of unirradiated hydrogen-charged nuclear fuel cladding from ring compression tests

In this work, a new methodology is devised to obtain the fracture properties of nuclear fuel cladding in the hoop direction. The proposed method combines ring compression tests and a finite element method that includes a damage model based on cohesive crack theory, applied to unirradiated hydrogen-charged ZIRLOTM nuclear fuel cladding. Samples with hydrogen concentrations from 0 to 2000 ppm were tested at 20 �C. Agreement between the finite element simulations and the experimental results is excellent in all cases. The parameters of the cohesive crack model are obtained from the simulations, with the fracture energy and fracture toughness being calculated in turn. The evolution of fracture toughness in the hoop direction with the hydrogen concentration (up to 2000 ppm) is reported for the first time for ZIRLOTM cladding. Additionally, the fracture micromechanisms are examined as a function of the hydrogen concentration. In the as-received samples, the micromechanism is the nucleation, growth and coalescence of voids, whereas in the samples with 2000 ppm, a combination of cuasicleavage and plastic deformation, along with secondary microcracking is observed.

A Semi-Lagrangian Particle Level Set Finite Element Method for Interface Problems

We present a quasi-monotone semi-Lagrangian particle level set (QMSL-PLS) method for moving interfaces. The QMSL method is a blend of first order monotone and second order semi-Lagrangian methods. The QMSL-PLS method is easy to implement, efficient, and well adapted for unstructured, either simplicial or hexahedral, meshes. We prove that it is unconditionally stable in the maximum discrete norm, � · �h,∞, and the error analysis shows that when the level set solution u(t) is in the Sobolev space Wr+1,∞(D), r ≥ 0, the convergence in the maximum norm is of the form (KT/Δt)min(1,Δt � v �h,∞ /h)((1 − α)hp + hq), p = min(2, r + 1), and q = min(3, r + 1),where v is a velocity. This means that at high CFL numbers, that is, when Δt > h, the error is O( (1−α)hp+hq) Δt ), whereas at CFL numbers less than 1, the error is O((1 − α)hp−1 + hq−1)). We have tested our method with satisfactory results in benchmark problems such as the Zalesak’s slotted disk, the single vortex flow, and the rising bubble.

Statistical distributions obtained from the compression of monodisperse, soft and frictionless particles

The cyclic compression of several granular systems has been simulated with a molecular dynamics code. All the samples consisted of bidimensional, soft, frictionless and equal-sized particles that were initially arranged according to a squared lattice and were compressed by randomly generated irregular walls. The compression protocols can be described by some control variables (volume or external force acting on the walls) and by some dimensionless factors, that relate stiffness, density, diameter, damping ratio and water surface tension to the external forces, displacements and periods. Each protocol, that is associated to a dynamic process, results in an arrangement with its own macroscopic features: volume (or packing ratio), coordination number, and stress; and the differences between packings can be highly significant. The statistical distribution of the force-moment state of the particles (i.e. the equivalent average stress multiplied by the volume) is analyzed. In spite of the lack of a theoretical framework based on statistical mechanics specific for these protocols, it is shown how the obtained distributions of mean and relative deviatoric force-moment are. Then it is discussed on the nature of these distributions and on their relation to specific protocols.

Long wave theory for experimental devices with compressed/expanded surfactant monolayers

Surfactant monolayers are of interest in a variety of phenomena, including thin film dynamics and the formation and dynamics of foams. Measurement of surface properties has received a continuous attention and requires good theoretical models to extract the relevant physico- chemical information from experimental data. A common experimental set up consists in a shallow liquid layer whose free surface is slowly com- pressed/expanded in periodic fashion by moving two slightly immersed solid barriers, which varies the free surface area and thus the surfactant concentration. The simplest theory ignores the fluid dynamics in the bulk fluid, assuming spatially uniform surfactant concentration, which requires quite small forcing frequencies and provides reversible dynamics in the compression/expansion cycles. Sometimes, it is not clear whether depar- ture from reversibility is due to non-equilibrium effects or to the ignored fluid dynamics. Here we present a long wave theory that takes the fluid dynamics and the symmetries of the problem into account. In particular, the validity of the spatially-uniform-surfactant-concentration assumption is established and a nonlinear diffusion equation is derived. This allows for calculating spatially nonuniform monolayer dynamics and uncovering the physical mechanisms involved in the surfactant behavior. Also, this analysis can be considered a good means for extracting more relevant information from each experimental run.

Nonlinear Dynamics in experimental devices with compressed/expanded surfactant monolayers

A theory is provided for a common experimental set up that is used to measure surface properties in surfactant monolayers. The set up consists of a surfactant monolayer (over a shallow liquid layer) that is compressed/expanded in a periodic fashion by moving in counter-phase two parallel, slightly immersed solid barriers, which vary the free surface area and thus the surfactant concentration. The simplest theory ignores the fluid dynamics in the bulk fluid, assuming spatially uniform surfactant concentration, which requires quite small forcing frequencies and provides reversible dynamics in the compression/expansion cycles. In this paper, we present a long-wave theory for not so slow oscillations that assumes local equilibrium but takes the fluid dynamics into account. This simple theory uncovers the physical mechanisms involved in the surfactant behavior and allows for extracting more information from each experimental run. The conclusion is that the fluid dynamics cannot be ignored, and that some irreversible dynamics could well have a fluid dynamic origin

Estudio de la permeabilidad y de la resistencia a tracción en hormigones precomprimidos

Entre los requisitos que deben cumplir las estructuras se debe garantizar que estas posean la durabilidad necesaria para permanecer en servicio a lo largo de todo el periodo de vida útil para el que han sido proyectadas. Para conseguir este objetivo las normativas han ido incorporando prescripciones para el diseño del hormigón, en base a distintas clases de exposición dependiendo del origen y magnitud de la agresividad exterior. En ambientes con una elevada agresividad, una de las comprobaciones que debe cumplir el hormigón es que tenga una permeabilidad inferior a los valores máximos fijados según la clase de exposición, y que en caso de considerar como ensayo de referencia el de penetración de agua, analiza el frente de penetración limitando las profundidades de penetración media y máxima. Adicionalmente a las condiciones de diseño según el tipo de ambiente, principalmente basadas en la dosificación del hormigón en términos de la relación agua/cemento y el mínimo contenido de cemento y el recubrimiento de las armaduras, durante la vida en servicio las estructuras pueden están solicitadas por distintas acciones imprevistas que pueden provocar cambios en la microestructura interna del hormigón que modifican su permeabilidad y resistencia, y por tanto pueden alterar la durabilidad inicialmente prevista. Es conocido el efecto de cansancio del hormigón cuando está solicitado por cargas de compresión mantenidas en el tiempo, provocando bajas en su resistencia debido al incremento de la microfisuración. Dada la relación entre la permeabilidad y la microfisuración del hormigón, es previsible el aumento de la permeabilidad en hormigones que han sido precomprimidos durante un periodo largo de tiempo. Los estudios de la permeabilidad en hormigones previamente comprimidos se han realizado analizando periodos de tiempo de compresión cortos que no permiten evaluar el efecto del cansancio sobre la permeabilidad. La presente tesis doctoral investiga la permeabilidad y resistencia a tracción en hormigones que previamente han sido comprimidos en carga mantenida durante distintos plazos de tiempo, al objeto de conocer su evolución en base al tiempo de precompresión. La investigación se apoya en el estudio de otras dos variables como son el tipo de hormigón de acuerdo a su dosificación según el tipo de ambiente considerando una agresividad baja, media o alta, y el grado de compresión aplicado respecto de su carga última de rotura. En los resultados del plan experimental desarrollado se ha obtenido que la permeabilidad presenta un incremento significante con el tiempo de precompresión, que dependiendo del valor inicial de la permeabilidad que tiene el hormigón puede provocar que hormigones que previamente satisfacen las limitaciones de permeabilidad pasen a incumplirlas, pudiendo afectar a su durabilidad. También se confirma la influencia del tiempo de precompresión sobre la resistencia a tracción obteniendo bajas de resistencia importantes en los casos pésimos ensayados, que deben ser tenidas en consideración en tanto afectan a la capacidad resistente del hormigón como a otros aspectos fundamentales como el anclaje de las armaduras en el hormigón armado y pretensado. One of the requirements that structures must meet is to guarantee their durability to remain in service throughout all the working life period for which they have been designed. To achieve this goal, building standards and codes have included specifications for the design of concrete structures, based on different exposure classes depending on the environmental conditions and their origin and magnitude. In severe aggressive environments, one of the specifications the concrete must meet is to have a permeability lower than the maximum values set for a certain exposure class. If this parameter is referenced to water penetration on specimens, then the average and maximum depths of front penetration are analyzed. In addition to the design conditions depending on the exposure class, which regulate the dosage of concrete in terms of the water/cement ratio, minimum samples that have been pre-compressed for a long period of time. Previous studies on permeability have been carried on pre-compressed concrete elements analyzing short periods of time. However, they have not studied the effects of compression forces on concrete in the long term. This Thesis investigates permeability and tensile strength of concrete samples that have been previously compressed under loads applied for different periods of time. The goal is to understand its evolution based on the time exposed to compression. The research variables also include the type of concrete according to the dosage used - depending on the environmental exposure it will have low, medium or high aggressiveness-, and the amount of compression applied in relation to its failure load. Results of the experimental tests showed that permeability increases significantly over the time of pre-compression. Depending on the initial value of permeability, this change could make the concrete not meet the original permeability restrictions and therefore affect its durability. These investigations also confirmed the influence of time of pre-compression in tensile strength, where some cases showed a significant decrease of resistance. These issues must be taken into consideration as they affect the bearing capacity of the material and other key features such as the anchoring of steel bars in reinforced and pre-stressed concrete. amount of cement content and the minimum concrete cover of the steel bars, during their working life structures may be subject to various unforeseen actions. As a result, the concrete’s internal microstructure might be affected, changing its permeability and resistance, and possibly altering the original specified durability. It is a known fact that when concrete is loaded in compression maintained over a long time, its resistance to compression forces is diminished due to the increase in micro-cracking. Considering the relationship between permeability and microcracking of concrete, an increase in permeability may be expected in concrete

Cálculo de pilas con aparatos de apoyo tipo POT y tablero con punto fijo

In recent years a great number of high speed railway bridges have been constructed within the Spanish borders. Due to the demanding high speed trains route's geometrical requirements, bridges frequently show remarkable lengths. This fact is the main reason why railway bridges are overall longer than roadway bridges. In the same line, it is also worth highlighting the importance of high speed trains braking forces compared to vehicles. While vehicles braking forces can be tackled easily, the railway braking forces demand the existence of a fixed-point. It is generally located at abutments where the no-displacements requirement can be more easily achieved. In some other cases the fixed-point is placed in one of the interior columns. As a consequence of these bridges' length and the need of a fixed-point, temperature, creep and shrinkage strains lead to fairly significant deck displacements, which become greater with the distance to the fixed-point. These displacements need to be accommodated by the piers and bearings deformation. Regular elastomeric bearings are not able to allow such displacements and therefore are not suitable for this task. For this reason, the use of sliding PTFE POT bearings has been an extensive practice mainly because they permit sliding with low friction. This is not the only reason of the extensive use of these bearings to high-speed railways bridges. The value of the vertical loads at each bent is significantly higher than in roadway bridges. This is so mainly because the live loads due to trains traffic are much greater than vehicles. Thus, gravel rails foundation represents a non-negligible permanent load at all. All this together increases the value of vertical loads to be withstood. This high vertical load demand discards the use of conventional bearings for excessive compressions. The PTFE POT bearings' higher technology allows to accommodate this level of compression thanks to their design. The previously explained high-speed railway bridge configuration leads to a key fact regarding longitudinal horizontal loads (such as breaking forces) which is the transmission of these loads entirely to the fixed-point alone. Piers do not receive these longitudinal horizontal loads since PTFE POT bearings displayed are longitudinally free-sliding. This means that longitudinal horizontal actions on top of piers will not be forces but imposed displacements. This feature leads to the need to approach these piers design in a different manner that when piers are elastically linked to superstructure, which is the case of elastomeric bearings. In response to the previous, the main goal of this Thesis is to present a Design Method for columns displaying either longitudinally fixed POT bearings or longitudinally free PTFE POT bearings within bridges with fixed-point deck configuration, applicable to railway and road vehicles bridges. The method was developed with the intention to account for all major parameters that play a role in these columns behavior. The long process that has finally led to the method's formulation is rooted in the understanding of these column's behavior. All the assumptions made to elaborate the formulations contained in this method have been made in benefit of conservatives results. The singularity of the analysis of columns with this configuration is due to a combination of different aspects. One of the first steps of this work was to study they of these design aspects and understand the role each plays in the column's response. Among these aspects, special attention was dedicated to the column's own creep due to permanent actions such us rheological deck displacements, and also to the longitudinally guided PTFE POT bearings implications in the design of the column. The result of this study is the Design Method presented in this Thesis, that allows to work out a compliant vertical reinforcement distribution along the column. The design of horizontal reinforcement due to shear forces is not addressed in this Thesis. The method's formulations are meant to be applicable to the greatest number of cases, leaving to the engineer judgement many of the different parameters values. In this regard, this method is a helpful tool for a wide range of cases. The widespread use of European standards in the more recent years, in particular the so-called Eurocodes, has been one of the reasons why this Thesis has been developed in accordance with Eurocodes. Same trend has been followed for the bearings design implications, which are covered by the rather recent European code EN-1337. One of the most relevant aspects that this work has taken from the Eurocodes is the non-linear calculations security format. The biaxial bending simplified approach that shows the Design Method presented in this work also lies on Eurocodes recommendations. The columns under analysis are governed by a set of dimensionless parameters that are presented in this work. The identification of these parameters is a helpful for design purposes for two columns with identical dimensionless parameters may be designed together. The first group of these parameters have to do with the cross-sectional behavior, represented in the bending-curvature diagrams. A second group of parameters define the columns response. Thanks to this identification of the governing dimensionless parameters, it has been possible what has been named as Dimensionless Design Curves, which basically allows to obtain in a reduced time a preliminary vertical reinforcement column distribution. These curves are of little use nowadays, firstly because each family of curves refer to specific values of many different parameters and secondly because the use of computers allows for extremely quick and accurate calculations.

A new set of integrals of motion to propagate the perturbed two-body problem

A formulation of the perturbed two-body problem that relies on a new set of orbital elements is presented. The proposed method represents a generalization of the special perturbation method published by Peláez et al. (Celest Mech Dyn Astron 97(2):131?150,2007) for the case of a perturbing force that is partially or totally derivable from a potential. We accomplish this result by employing a generalized Sundman time transformation in the framework of the projective decomposition, which is a known approach for transforming the two-body problem into a set of linear and regular differential equations of motion. Numerical tests, carried out with examples extensively used in the literature, show the remarkable improvement of the performance of the new method for different kinds of perturbations and eccentricities. In particular, one notable result is that the quadratic dependence of the position error on the time-like argument exhibited by Peláez?s method for near-circular motion under the J2 perturbation is transformed into linear.Moreover, themethod reveals to be competitive with two very popular elementmethods derived from theKustaanheimo-Stiefel and Sperling-Burdet regularizations.