a-SiCH Based Devices as Optical Demultiplexers

In this paper we present results on the use of a multilayered a-SiC:H heterostructure as a wavelength-division demultiplexing device (WDM) for the visible light spectrum. The WDM device is a glass/ITO/a-SiC:H (p-i-n)/ a-SiC:H(-p) /Si:H(-i)/SiC:H (-n)/ITO heterostructure in which the generated photocurrent at different values of the applied bias can be assigned to the different optical signals. The device was characterized through spectral response measurements, under different electrical bias. Demonstration of the device functionality for WDM applications was done with three different input channels covering wavelengths within the visible range. The recovery of the input channels is explained using the photocurrent spectral dependence on the applied voltage. The influence of the optical power density was also analysed. An electrical model, supported by a numerical simulation explains the device operation. Short range optical communications constitute the major application field, however other applications are also foreseen.

Avaliação de qualidade de energia de um sistema fotovoltaico numa rede elétrica

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Energia

Implementação de WDM com 4 canais no espetro do visível

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Study of Annealed Indium Tin Oxide-Films prepared by RF Reactive Magnetron Sputtering

Tin doped indium oxide (ITO) films were deposited on glass substrates by rf reactive magnetron sputtering using a metallic alloy target (In-Sn, 90-10). The post-deposition annealing has been done for ITO films in air and the effect of annealing temperature on the electrical, optical and structural properties of ITO films was studied. It has been found that the increase of the annealing temperature will improve the film electrical properties. The resistivity of as deposited film is about 1.3 x 10(-1) Omega*cm and decreases down to 6.9 x 10(-3) Omega*cm as the annealing temperature is increased up to 500 degrees C. In addition, the annealing will also increase the film surface roughness which can improve the efficiency of amorphous silicon solar cells by increasing the amount of light trapping.

Vertical CNT-Si Photodiode Array

Agências financiadoras: National Natural Science Foundation of China - 61204077; Shenzhen Science and Technology Innovation Commission - JCYJ20120614150521967

Facile synthesis of freestanding Si nanowire arrays by one-step template-free electro-deoxidation of SiO2 in molten salt

This communication presents a novel kind of silicon nanomaterial: freestanding Si nanowire arrays (Si NWAs), which are synthesized facilely by one-step template-free electro-deoxidation of SiO2 in molten CaCl2. The self-assembling growth process of this material is also investigated preliminarily.

Sistema WDM de 4 canais

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Self-mated tribological systems based on multilayer micro/nanocrystalline CVD diamond coatings

The tribological response of multilayer micro/nanocrystalline diamond coatings grown by the hot filament CVD technique is investigated. These multigrade systems were tailored to comprise a starting microcrystalline diamond (MCD) layer with high adhesion to a silicon nitride (Si3N4) ceramic substrate, and a top nanocrystalline diamond (NCD) layer with reduced surface roughness. Tribological tests were carried out with a reciprocating sliding configuration without lubrication. Such composite coatings exhibit a superior critical load before delamination (130–200 N), when compared to the mono- (60–100 N) and bilayer coatings (110 N), considering ∼10 µm thick films. Regarding the friction behaviour, a short-lived initial high friction coefficient was followed by low friction regimes (friction coefficients between 0.02 and 0.09) as a result of the polished surfaces tailored by the tribological solicitation. Very mild to mild wear regimes (wear coefficient values between 4.1×10−8 and 7.7×10−7 mm3 N−1 m−1) governed the wear performance of the self-mated multilayer coatings when subjected to high-load short-term tests (60–200 N; 2 h; 86 m) and medium-load endurance tests (60 N; 16 h; 691 m).

A tecnologia fotovoltaica de película fina. Afinal como estamos?

Todos nós estamos familiarizados com os painéis fotovoltaicos comuns, os silicon wafer-based (“bolacha/pastilha” de silício), que possuem atualmente uma quota superior a 80% [1-3] no mercado solar fotovoltaico. Desde o seu “aparecimento” em 1950, foram realizados avanços em diferentes vertentes, como a eficiência, durabilidade, custos e tecnologias de produção [2, 4, 5], sendo que no início deste século se começaram a desenvolver e a criar expectativas positivas crescentes acerca do que se designa de células fotovoltaicas de película fina ou TFPC (thin film photovoltaic cells). Certamente, já todos ouvimos notícias nos últimos anos do seu desenvolvimento e de aplicações variadas (vestuário, fachadas, etc), pelo que este artigo visa elucidar o leitor acerca do que são, do seu grau de investigação e desenvolvimento (I&D) e da posição no mercado atual e futura.

Enhanced Race-to-halt: a leakage-aware energy management approach for dynamic priority systems

With progressing CMOS technology miniaturization, the leakage power consumption starts to dominate the dynamic power consumption. The recent technology trends have equipped the modern embedded processors with the several sleep states and reduced their overhead (energy/time) of the sleep transition. The dynamic voltage frequency scaling (DVFS) potential to save energy is diminishing due to efficient (low overhead) sleep states and increased static (leakage) power consumption. The state-of-the-art research on static power reduction at system level is based on assumptions that cannot easily be integrated into practical systems. We propose a novel enhanced race-to-halt approach (ERTH) to reduce the overall system energy consumption. The exhaustive simulations demonstrate the effectiveness of our approach showing an improvement of up to 8 % over an existing work.

Modular high-current generator for electromagnetic forming with energy recovery

A 10 kJ electromagnetic forming (EMF) modulator with energy recovery based on two resonant power modules, each containing a 4.5 kV/30-kA silicon controlled rectifier, a 1.11-mF capacitor bank and an energy recovery circuit, working in parallel to allow a maximum actuator discharge current amplitude and rate of 50 kA and 2 kA/mu s was successfully developed and tested. It can be plugged in standard single phase 230 V/16 A mains socket and the circuit is able to recover up to 32% of its initial energy, reducing the charging time of conventional EMF systems by up to 68%.

Role of abrasive material on micro-abrasion wear tests

Micro-abrasion wear tests with ball-cratering configuration are widely used. Sources of variability are already studied by different authors and conditions for testing are parameterized by BS EN 1071-6: 2007 standard which refers silicon carbide as abrasive. However, the use of other abrasives is possible and allowed. In this work, ball-cratering wear tests were performed using four different abrasive particles of three dissimilar materials: diamond, alumina and silicon carbide. Tests were carried out under the same conditions on a steel plate provided with TiB2 hard coating. For each abrasive, five different test durations were used allowing understanding the initial wear phenomena. Composition and shape of abrasive particles were investigated by SEM and EDS. Scar areas were observed by optical and electronic microscopy in order to understand the wear effects caused by each of them. Scar geometry and grooves were analyzed and compared. Wear coefficient was calculated for each situation. It was observed that diamond particles produce well-defined and circular wear scars. Different silicon carbide particles presented dissimilar results as consequence of distinct particle shape and size distribution.

A Design methodology for integrated inductor-based DC-DC converters

A design methodology for monolithic integration of inductor based DC-DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 mu m CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.

Demux devices based on A-SiC:H

In this paper we present results about the functioning of a multilayered a-SiC:H heterostructure as a device for wavelength-division demultiplexing of optical signals. The device is composed of two stacked p-i-n photodiodes, both optimized for the selective collection of photogenerated carriers. Band gap engineering was used to adjust the photogeneration and recombination rates profiles of the intrinsic absorber regions of each photodiode to short and long wavelength absorption and carrier collection in the visible spectrum. The photocurrent signal using different input optical channels was analyzed at reverse and forward bias and under steady state illumination. This photocurrent is used as an input for a demux algorithm based on the voltage controlled sensitivity of the device. The device functioning is explained with results obtained by numerical simulation of the device, which permit an insight to the internal electric configuration of the double heterojunction.These results address the explanation of the device functioning in the frequency domain to a wavelength tunable photocapacitance due to the accumulation of space charge localized at the internal junction. The existence of a direct relation between the experimentally observed capacitive effects of the double diode and the quality of the semiconductor materials used to form the internal junction is highlighted.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.