Physical Layer Security with Threshold-Based Multiuser Scheduling in Multi-antenna Wireless Networks

In this paper, we consider a multiuser downlink wiretap network consisting of one base station (BS) equipped with AA antennas, NB single-antenna legitimate users, and NE single-antenna eavesdroppers over Nakagami-m fading channels. In particular, we introduce a joint secure transmission scheme that adopts transmit antenna selection (TAS) at the BS and explores threshold-based selection diversity (tSD) scheduling over legitimate users to achieve a good secrecy performance while maintaining low implementation complexity. More specifically, in an effort to quantify the secrecy performance of the considered system, two practical scenarios are investigated, i.e., Scenario I: the eavesdropper’s channel state information (CSI) is unavailable at the BS, and Scenario II: the eavesdropper’s CSI is available at the BS. For Scenario I, novel exact closed-form expressions of the secrecy outage probability are derived, which are valid for general networks with an arbitrary number of legitimate users, antenna configurations, number of eavesdroppers, and the switched threshold. For Scenario II, we take into account the ergodic secrecy rate as the principle performance metric, and derive novel closed-form expressions of the exact ergodic secrecy rate. Additionally, we also provide simple and asymptotic expressions for secrecy outage probability and ergodic secrecy rate under two distinct cases, i.e., Case I: the legitimate user is located close to the BS, and Case II: both the legitimate user and eavesdropper are located close to the BS. Our important findings reveal that the secrecy diversity order is AAmA and the slope of secrecy rate is one under Case I, while the secrecy diversity order and the slope of secrecy rate collapse to zero under Case II, where the secrecy performance floor occurs. Finally, when the switched threshold is carefully selected, the considered scheduling scheme outperforms other well known existing schemes in terms of the secrecy performance and complexity tradeoff

Applications of Microwave Antenna Array for Wireless Power Transmission and Radar Imaging in Complex Environment

Thesis (Ph.D.)--University of Washington, 2016-08

High performance terahertz resonant tunnelling diode sources and broadband antenna for air-side radiation

Resonant tunnelling diode (RTD) is known to be the fastest electronics device that can be fabricated in compact form and operate at room temperature with potential oscillation frequency up to 2.5 THz. The RTD device consists of a narrow band gap quantum well layer sandwiched between two thin wide band gap barriers layers. It exhibits negative differential resistance (NDR) region in its current-voltage (I-V) characteristics which is utilised in making oscillators. Up to date, the main challenge is producing high output power at high frequencies in particular. Although oscillation frequencies of ~ 2 THz have been already reported, the output power is in the range of micro-Watts. This thesis describes the systematic work on the design, fabrication, and characterisation of RTD-based oscillators in microwave/millimetre-wave monolithic integrated circuits (MMIC) form that can produce high output power and high oscillation frequency at the same time. Different MMIC RTD oscillator topologies were designed, fabricated, and characterised in this project which include: single RTD oscillator which employs one RTD device, double RTDs oscillator which employs two RTD devices connected in parallel, and coupled RTD oscillators which combine the powers of two oscillators over a single load, based on mutual coupling and which can employ up to four RTD devices. All oscillators employed relatively large size RTD devices for high power operation. The main challenge was to realise high oscillation frequency (~ 300 GHz) in MMIC form with the employed large sized RTD devices. To achieve this aim, proper designs of passive structures that can provide small values of resonating inductances were essential. These resonating inductance structures included shorted coplanar wave guide (CPW) and shorted microstrip transmission lines of low characteristics impedances Zo. Shorted transmission line of lower Zo has lower inductance per unit length. Thus, the geometrical dimensions would be relatively large and facilitate fabrication by low cost photolithography. A series of oscillators with oscillation frequencies in the J-band (220 – 325 GHz) range and output powers from 0.2 – 1.1 mW have been achieved in this project, and all were fabricated using photolithography. Theoretical estimation showed that higher oscillation frequencies (> 1 THz) can be achieved with the proposed MMIC RTD oscillators design in this project using photolithography with expected high power operation. Besides MMIC RTD oscillators, reported planar antennas for RTD-based oscillators were critically reviewed and the main challenges in designing high performance integrated antennas on large dielectric constant substrates are discussed in this thesis. A novel antenna was designed, simulated, fabricated, and characterised in this project. It was a bow-tie antenna with a tuning stub that has very wide bandwidth across the J-band. The antenna was diced and mounted on a reflector ground plane to alleviate the effect of the large dielectric constant substrate (InP) and radiates upwards to the air-side direction. The antenna was also investigated for integration with the all types of oscillators realised in this project. One port and two port antennas were designed, simulated, fabricated, and characterised and showed the suitability of integration with the single/double oscillator layout and the coupled oscillator layout, respectively.

A future dynamically reconfigurable automotive software system

Embedded software systems in vehicles are of rapidly increasing commercial importance for the automotive industry. Current systems employ a static run-time environment; due to the difficulty and cost involved in the development of dynamic systems in a high-integrity embedded control context. A dynamic system, referring to the system configuration, would greatly increase the flexibility of the offered functionality and enable customised software configuration for individual vehicles, adding customer value through plug-and-play capability, and increased quality due to its inherent ability to adjust to changes in hardware and software. We envisage an automotive system containing a variety of components, from a multitude of organizations, not necessarily known at development time. The system dynamically adapts its configuration to suit the run-time system constraints. This paper presents our vision for future automotive control systems that will be regarded in an EU research project, referred to as DySCAS (Dynamically Self-Configuring Automotive Systems). We propose a self-configuring vehicular control system architecture, with capabilities that include automatic discovery and inclusion of new devices, self-optimisation to best-use the processing, storage and communication resources available, self-diagnostics and ultimately self-healing. Such an architecture has benefits extending to reduced development and maintenance costs, improved passenger safety and comfort, and flexible owner customisation. Specifically, this paper addresses the following issues: The state of the art of embedded software systems in vehicles, emphasising the current limitations arising from fixed run-time configurations; and the benefits and challenges of dynamic configuration, giving rise to opportunities for self-healing, self-optimisation, and the automatic inclusion of users’ Consumer Electronic (CE) devices. Our proposal for a dynamically reconfigurable automotive software system platform is outlined and a typical use-case is presented as an example to exemplify the benefits of the envisioned dynamic capabilities.

Bull's eye leaky wave antenna for terrestrial and space applications

This work presents the study of Bull's eye antenna designs, a type of leaky wave antenna (LWA), operating in the 60 GHz band. This band emerged as a new standard for specific terrestrial and space applications because the radio spectrumbecomes more congested up to the millimetre-wave band, starting at 30 GHz. Built on existing Bull's eye antenna designs, novel structures were simulated, fabricated and measured, so as to provide more exibility in the implementation of wireless solutions at this frequency. Firstly, the study of a 60 GHz Bull's eye antenna for straightforward integration onto a CubeSat is presented. An investigation of the design is carried out, from the description of the radiation mechanism supported by simulation results, to the radiation pattern measurement of a prototype which provides a gain of 19.1 dBi at boresight. Another design, based on a modified feed structure, uses a microstrip to waveguide transition to provide easier and inexpensive integration of a Bull's eye antenna onto a planar circuit. Secondly, the design of Bull's eye antennas capable of creating beam deflection and multi-beam is presented. In particular, a detail study of the deflection mechanism is proposed, followed by the demonstration of a Bull's eye antenna generating two separate beams at ±16° away from the boresight. In addition, a novel mechanically steerable Bull's eye antenna, based on the division of the corrugated area in paired sectors is presented. A prototype was fabricated and measured. It generated double beams at ±8° and ±15° from the boresight, and a single boresight beam. Thirdly, a Bull's eye antenna capable of generating two simultaneous orbital angular momentum (OAM) modes l = 3 is proposed. The design is based on a circular travelling wave resonator and would allow channel capacity increase through OAM multiplexing. An improved design based on two stacked OAM Bull's eye antennas capable of producing four orthogonal OAM modes l = (±3,±13) simultaneously is presented. A novel receiving scheme based on discretely sampled partial aperture receivers (DSPAR) is then introduced. This solution could provide a lower windage and a lower cost of implementation than current whole or partial continuous aperture.

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems

Dynamically reconfigurable hardware is a promising technology that combines in the same device both the high performance and the flexibility that many recent applications demand. However, one of its main drawbacks is the reconfiguration overhead, which involves important delays in the task execution, usually in the order of hundreds of milliseconds, as well as high energy consumption. One of the most powerful ways to tackle this problem is configuration reuse, since reusing a task does not involve any reconfiguration overhead. In this paper we propose a configuration replacement policy for reconfigurable systems that maximizes task reuse in highly dynamic environments. We have integrated this policy in an external taskgraph execution manager that applies task prefetch by loading and executing the tasks as soon as possible (ASAP). However, we have also modified this ASAP technique in order to make the replacements more flexible, by taking into account the mobility of the tasks and delaying some of the reconfigurations. In addition, this replacement policy is a hybrid design-time/run-time approach, which performs the bulk of the computations at design time in order to save run-time computations. Our results illustrate that the proposed strategy outperforms other state-ofthe-art replacement policies in terms of reuse rates and achieves near-optimal reconfiguration overhead reductions. In addition, by performing the bulk of the computations at design time, we reduce the execution time of the replacement technique by 10 times with respect to an equivalent purely run-time one.

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on As-Soon-As-Possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This paper proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this paper proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This paper also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

HW implementation of an execution manager for reconfigurable systems

Reconfigurable HW can be used to build a hardware multitasking system where tasks can be assigned to the reconfigurable HW at run-time according to the requirements of the running applications. Normally the execution in this kind of systems is controlled by an embedded processor. In these systems tasks are frequently represented as subtask graphs, where a subtask is the basic scheduling unit that can be assigned to a reconfigurable HW. In order to control the execution of these tasks, the processor must manage at run-time complex data structures, like graphs or linked list, which may generate significant execution-time penalties. In addition, HW/SW communications are frequently a system bottleneck. Hence, it is very interesting to find a way to reduce the run-time SW computations and the HW/SW communications. To this end we have developed a HW execution manager that controls the execution of subtask graphs over a set of reconfigurable units. This manager receives as input a subtask graph coupled to a subtask schedule, and guarantees its proper execution. In addition it includes support to reduce the execution-time overhead due to reconfigurations. With this HW support the execution of task graphs can be managed efficiently generating only very small run-time penalties.

A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems

Reconfigurable hardware can be used to build a multitasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs and their execution is typically controlled by an embedded processor that schedules the graph execution. In order to improve the efficiency of the system, the scheduler can apply prefetch and reuse techniques that can greatly reduce the reconfiguration latencies. For an embedded processor all these computations represent a heavy computational load that can significantly reduce the system performance. To overcome this problem we have implemented a HW scheduler using reconfigurable resources. In addition we have implemented both prefetch and replacement techniques that obtain as good results as previous complex SW approaches, while demanding just a few clock cycles to carry out the computations. We consider that the HW cost of the system (in our experiments 3% of a Virtex-II PRO xc2vp30 FPGA) is affordable taking into account the great efficiency of the techniques applied to hide the reconfiguration latency and the negligible run-time penalty introduced by the scheduler computations.

An Approach to Manage Reconfigurations and Reduce Area Cost in Hard Real-Time Reconfigurable Systems

This article presents a methodology to build real-time reconfigurable systems that ensure that all the temporal constraints of a set of applications are met, while optimizing the utilization of the available reconfigurable resources. Starting from a static platform that meets all the real-time deadlines, our approach takes advantage of run-time reconfiguration in order to reduce the area needed while guaranteeing that all the deadlines are still met. This goal is achieved by identifying which tasks must be always ready for execution in order to meet the deadlines, and by means of a methodology that also allows reducing the area requirements.

A Task-Graph Execution Manager for Reconfigurable Multi-tasking Systems

Reconfigurable hardware can be used to build multi tasking systems that dynamically adapt themselves to the requirements of the running applications. This is especially useful in embedded systems, since the available resources are very limited and the reconfigurable hardware can be reused for different applications. In these systems computations are frequently represented as task graphs that are executed taking into account their internal dependencies and the task schedule. The management of the task graph execution is critical for the system performance. In this regard, we have developed two dif erent versions, a software module and a hardware architecture, of a generic task-graph execution manager for reconfigurable multi-tasking systems. The second version reduces the run-time management overheads by almost two orders of magnitude. Hence it is especially suitable for systems with exigent timing constraints. Both versions include specific support to optimize the reconfiguration process.