935 resultados para Graphics hardware
Resumo:
Three compounds have been found to be stable in the pseudobinary system Na2O---(α)Al2O3 between 825 and 1400 K; two nonstoichiometric phases, β-alumina and β″-alumina, and NaAlO2. The homogeneity of β-alumina ranges from 9.5 to 11 mol% Na2O, while that of β″-alumina from 13.3 to 15.9 mol% Na2O at 1173 K. The activity of Na2O in the two-phase fields has been determined by a solid-state potentiometric technique. Since both β- and β″-alumina are fast sodium ion conductors, biphasic solid electrolyte tubes were used in these electrochemical measurements. The open circuit emf of the following cells were measured from 790 to 980 K: [GRAPHICS] The partial molar Gibbs' energy of Na2O relative to gamma-Na2O in the two-phase regions can be represented as: DELTA-GBAR(Na2O)(alpha- + beta-alumina) = -270,900 + 24.03 T, DELTA-GBAR(Na2O)(beta- + beta"-alumina) = -232,700 + 56.19 T, and DELTA-GBAR(Na2O)(beta"-alumina + NaAlO2) = -13,100 - 4.51 T J mol-1. Similar galvanic cells using a Au-Na alloy and a mixture of Co + CoAl(2+2x)O4+3x + (alpha)Al2O3 as electrodes were used at 1400 K. Thermodynamic data obtained in these studies are used to evaluate phase relations and partial pressure of sodium in the Na2O-(alpha) Al2O3 system as a function of oxygen partial pressure, composition and temperature.
Resumo:
The formation and decomposition of quasicrystalline and crystalline phases in as-rapidly solidified and annealed commercial AISI 2024 aluminum alloy containing 2 wt% Li have been investigated by detailed transmission electron microscopy, including a combination of bright field and dark field imaging, selected area diffraction pattern analysis and energy dispersive X-ray microanalysis. The microstructure of as-melt spun 2024-2Li consists of alpha-Al cells, containing small coherent delta' precipitates, and particles or a continuous network of the icosahedral phase at the cell boundaries. After annealing at 300-degrees-C, the intercellular particles of the icosahedral phase coarsen progressively and assume a more faceted shape; after annealing at 400-degrees-C, particles of the decagonal and crystalline O phases precipitate heterogeneously on preexisting particles of the icosahedral phase; and after annealling at 500-degrees-C, the icosahedral and decagonal phases dissolve completely, and small particles of the crystalline O phase remain together with newly precipitated plates of the T1 phase. The icosahedral phase in melt spun and melt spun/annealed 2024-2Li belongs to the Al6CuLi3 class of icosahedral phases, with a quasilattice constant of 0.51 nm, a stoichiometry of (Al, Si)6(Cu, Mn, Fe) (Li, Mg)3 and an average composition of Al-24.1 at.% Cu-6.4 at.% Mg-1.7 at.% Si-0.3 at.% Mn-0.5 at.% Fe as-melt spun and Al-21.9 at.% Cu-6.3 at.% Mg-1.0 at.% Si-0.5 at.% Fe as-heat-treated. The decagonal phase in melt spun/annealed 2024-2Li belongs to the Al4Mn class of decagonal phases, with a periodicity of 1.23 nm along the 10-fold symmetry axis, a stoichiometry of Al3(Cu, Mn, Fe) and an average composition of Al-10.3 at.% Cu-13.8 at.% Mn-2.3 at.% Fe. The crystalline O phase in melt spun/annealed 2024-2Li has an orthorhombic structure with lattice parameters of a = 2.24 nm, b = 2.35 nm and c = 1.23 nm, a stoichiometry of Al3(Cu, Mn, Fe) and an average composition of Al-11.0 at.% Cu-14.8 at.% Mn-3.9 at.% Fe. Detailed analysis of selected area diffraction patterns shows a close similarity between the icosahedral, decagonal and crystalline O phases in melt spun and melt spun/annealed 2024-2Li. In particular, the decagonal phase and crystalline O phases have a similar composition, and exhibit an orientation relationship which can be expressed as: [GRAPHICS] suggesting that the orthorhombic O phase is an approximant structure for the decagonal phase.
Resumo:
With the advent of VLSI it has become possible to map parallel algorithms for compute-bound problems directly on silicon. Systolic architecture is very good candidate for VLSI implementation because of its regular and simple design, and regular communication pattern. In this paper, a systolic algorithm and corresponding systolic architecture, a linear systolic array, for the scanline-based hidden surface removal problem in three-dimensional computer graphics have been proposed. The algorithm is based on the concept of sample spans or intervals. The worst case time taken by the algorithm is O(n), n being the number of segments in a scanline. The time taken by the algorithm for a given scene depends on the scene itself, and on an average considerable improvement over the worst case behaviour is expected. A pipeline scheme for handling the I/O process has also been proposed which is suitable for VLSI implementation of the algorithm.
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We introduce a variation density function that profiles the relationship between multiple scalar fields over isosurfaces of a given scalar field. This profile serves as a valuable tool for multifield data exploration because it provides the user with cues to identify interesting isovalues of scalar fields. Existing isosurface-based techniques for scalar data exploration like Reeb graphs, contour spectra, isosurface statistics, etc., study a scalar field in isolation. We argue that the identification of interesting isovalues in a multifield data set should necessarily be based on the interaction between the different fields. We demonstrate the effectiveness of our approach by applying it to explore data from a wide variety of applications.
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The technical developments and advances that have taken place thus far are reviewed in those areas impacting future phased array active aperture radar systems. The areas covered are printed circuit antennas and antenna arrays, GaAs MMIC design and fabrication leading to affordable transmitter-receiver (T-R) modules, and novel hardware and software developments. The use of fiber-optic distribution networks to interconnect the monolithically integrated optical components with the T-R modules is discussed. Beamforming and sidelobe control techniques for active phased array systems are also examined.
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Implementation details of efficient schemes for lenient execution and concurrent execution of re-entrant routines in a data flow model have been discussed in this paper. The proposed schemes require no extra hardware support and utilise the existing hardware resources such as the Matching Unit and Memory Network Interface, effectively to achieve the above mentioned goals.
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Three dimensional clipping is a critical component of the 3D graphics pipeline. A new 3D clipping algorithm is presented in this paper. An efficient 2D clipping routine reported earlier has been used as a submodule. This algorithm uses a new classification scheme for lines of all possible orientations with respect to a rectangular parallelopiped view volume. The performance of this algorithm has been evaluated using exact arithmetic operation counts. It is shown that our algorithm requires less arithmetic operations than the Cyrus-Beck 3D clipping algorithm in all cases. It is also shown that for lines that intersect the clipping volume, our algorithm performs better than the Liang-Barsky 3D clipping algorithm.
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Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file. We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine. (C) 2010 Elsevier B.V. All rights reserved.
Resumo:
In this article we describe and demonstrate the versatility of a computer program, GENOME MAPPING, that uses interactive graphics and runs on an IRIS workstation. The program helps to visualize as well as analyse global and local patterns of genomic DNA sequences. It was developed keeping in mind the requirements of the human genome sequencing programme, which requires rapid analysis of the data. Using GENOME MAPPING one can discern signature patterns of different kinds of sequences and analyse such patterns for repetitive as well as rare sequence strings. Further, one can visualize the extent of global homology between different genomic sequences. An application of our method to the published yeast mitochondrial genome data shows similar sequence organizations in the entire sequence and in smaller subsequences.
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It is possible to sample signals at sub-Nyquist rate and still be able to reconstruct them with reasonable accuracy provided they exhibit local Fourier sparsity. Underdetermined systems of equations, which arise out of undersampling, have been solved to yield sparse solutions using compressed sensing algorithms. In this paper, we propose a framework for real time sampling of multiple analog channels with a single A/D converter achieving higher effective sampling rate. Signal reconstruction from noisy measurements on two different synthetic signals has been presented. A scheme of implementing the algorithm in hardware has also been suggested.
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A software and a microprocessor based hardware for waveform synthesis using Walsh functions are described. The software is based on Walsh function generation using Hadamard matrices and on the truncated Walsh series expansion for the waveform to be synthesized. The hardware employs six microprocessor controlled programmable Walsh function generators (PWFGs) for generating the first six non-vanishing terms of the truncated Walsh series. Improved approximation to a given waveform may be achieved by employing additional PWFGs.
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This paper presents a fast algorithm for data exchange in a network of processors organized as a reconfigurable tree structure. For a given data exchange table, the algorithm generates a sequence of tree configurations in which the data exchanges are to be executed. A significant feature of the algorithm is that each exchange is executed in a tree configuration in which the source and destination nodes are adjacent to each other. It has been proved in a theorem that for every pair of nodes in the reconfigurable tree structure, there always exists two and only two configurations in which these two nodes are adjacent to each other. The algorithm utilizes this fact and determines the solution so as to optimize both the number of configurations required and the time to perform the data exchanges. Analysis of the algorithm shows that it has linear time complexity, and provides a large reduction in run-time as compared to a previously proposed algorithm. This is well-confirmed from the experimental results obtained by executing a large number of randomly-generated data exchange tables. Another significant feature of the algorithm is that the bit-size of the routing information code is always two bits, irrespective of the number of nodes in the tree. This not only increases the speed of the algorithm but also results in simpler hardware inside each node.
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Two new line clipping algorithms, the opposite-corner algorithm and the perpendicular-distance algorithm, that are based on simple geometric observations are presented. These algorithms do not require computation of outcodes nor do they depend on the parametric representations of the lines. It is shown that the opposite-corner algorithm perform consistently better than an algorithm due to Nicholl, Lee, and Nicholl which is claimed to be better than the classic algorithm due to Cohen-Sutherland and the more recent Liang-Barsky algorithm. The pseudo-code of the opposite-corner algorithm is provided in the Appendix.
Resumo:
Memory models of shared memory concurrent programs define the values a read of a shared memory location is allowed to see. Such memory models are typically weaker than the intuitive sequential consistency semantics to allow efficient execution. In this paper, we present WOMM (abbreviation for Weak Operational Memory Model) that formally unifies two sources of weak behavior in hardware memory models: reordering of instructions and weakly consistent memory. We show that a large number of optimizations are allowed by WOMM. We also show that WOMM is weaker than a number of hardware memory models. Consequently, if a program behaves correctly under WOMM, it will be correct with respect to those hardware memory models. Hence, WOMM can be used as a formally specified abstraction of the hardware memory models. Moreover; unlike most weak memory models, WOMM is described using operational semantics, making it easy to integrate into a model checker for concurrent programs. We further show that WOMM has an important property - it has sequential consistency semantics for datarace-free programs.
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A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.