Energy Optimization of Memory Intensive Parallel Workloads

Energy consumption is an important concern in modern multicore processors. The energy consumed by a multicore processor during the execution of an application can be minimized by tuning the hardware state utilizing knobs such as frequency, voltage etc. The existing theoretical work on energy minimization using Global DVFS (Dynamic Voltage and Frequency Scaling), despite being thorough, ignores the time and the energy consumed by the CPU on memory accesses and the dynamic energy consumed by the idle cores. This article presents an analytical energy-performance model for parallel workloads that accounts for the time and the energy consumed by the CPU chip on memory accesses in addition to the time and energy consumed by the CPU on CPU instructions. In addition, the model we present also accounts for the dynamic energy consumed by the idle cores. The existing work on global DVFS for parallel workloads shows that using a single frequency for the entire duration of a parallel application is not energy optimal and that varying the frequency according to the changes in the parallelism of the workload can save energy. We present an analytical framework around our energy-performance model to predict the operating frequencies (that depend upon the amount of parallelism) for global DVFS that minimize the overall CPU energy consumption. We show how the optimal frequencies in our model differ from the optimal frequencies in a model that does not account for memory accesses. We further show how the memory intensity of an application affects the optimal frequencies.

Managed Acceleration for In-Memory Database Analytic Workloads

In-Memory Databases (IMDBs), such as SAP HANA, enable new levels of database performance by removing the disk bottleneck and by compressing data in memory. The consequence of this improved performance means that reports and analytic queries can now be processed on demand. Therefore, the goal is now to provide near real-time responses to compute and data intensive analytic queries. To facilitate this, much work has investigated the use of acceleration technologies within the database context. While current research into the application of these technologies has yielded positive results, they have tended to focus on single database tasks or on isolated single user requests. This paper uses SHEPARD, a framework for managing accelerated tasks across shared heterogeneous resources, to introduce acceleration into an IMDB. Results show how, using SHEPARD, multiple simultaneous user queries all receive speed-up by using a shared pool of accelerators. Results also show that offloading analytic tasks onto accelerators can have indirect benefits for other database workloads by reducing contention for CPU resources.

Does final demand for energy in Portugal exhibit long memory

In this paper, we measure the degree of fractional integration in final energy demand in Portugal using an ARFIMA model with and without adjustments for seasonality. We consider aggregate energy demand as well as final demand for petroleum, electricity, coal, and natural gas. Our findings suggest the presence of long memory in all of the energy demand variables, that the series are stationary, although the mean reversion process will be slower than in the typical short run processes. These results have important implications for the design of energy policies. The effects of temporary policy shocks on final energy demand will tend to disappear slowly. This means that even transitory shocks have long lasting effects. Given the temporary nature of these effects, however, permanent effects require permanent policies. This is unlike what would be suggested by the more standard but much more limited unit root approach, which would incorrectly indicate that even transitory policies would have permanent effects.

Present, imagination and memory in Zakes Mda and Mia Couto

Apesar de marcadas por contextos históricos e culturais distintos, é possível observar nas obras de dois dos autores mais significativos da África do Sul e de Moçambique, Zakes Mda e Mia Couto respectivamente, perspectivas semelhantes no que diz respeito à recuperação das memórias históricoculturais e à sua contribuição para a construção e compreensão das identidades pós-coloniais. Através da ficção, Zakes Mda e Mia Couto combinam a ligação da História a factos concretos com a necessidade de revelação associada à memória, criando assim espaços importantes para a discussão de algumas das mais complexas questões colocadas às identidades pós-coloniais. Para além dos contextos políticos, culturais e históricos que caracterizam e distinguem as literaturas sul-africana e moçambicana, tanto Zakes Mda como Mia Couto assumem nas suas obras a necessidade de analisar as identidades pós-coloniais contemporâneas dos dois países através da recuperação das suas memórias históricas.

The work of memory: embodiment, materiality and home in Jeanne Bouvier’s autobiographical writings

In this paper I follow trails in the memory of work by reading the books and papers of Jeanne Bouvier, a French seamstress, ardent trade-unionist and passionate writer, who left a rich body of labour literature including four published historical studies, as well as the memoirs of her life, work and struggles. Work, action and creativity are three interrelated planes on which Bouvier situates herself, while memory and imagination are interwoven in the way she seeks to understand herself in the world with others. What emerges as a particularly striking theme from Bouvier’s papers is a material matrix of mnemonic and imaginary practices, wherein bodies, places and objects are entangled in the narrative constitution of the self of the woman worker/writer.

Electrical characterization of metal-oxide-polymer devices for non-volatile memory applications

The objective of this thesis is to study the properties of resistive switching effect based on bistable resistive memory which is fabricated in the form of Al2O3/polymer diodes and to contribute to the elucidation of resistive switching mechanisms. Resistive memories were characterized using a variety of electrical techniques, including current-voltage measurements, small-signal impedance, and electrical noise based techniques. All the measurements were carried out over a large temperature range. Fast voltage ramps were used to elucidate the dynamic response of the memory to rapid varying electric fields. The temperature dependence of the current provided insight into the role of trapped charges in resistive switching. The analysis of fast current fluctuations using electric noise techniques contributed to the elucidation of the kinetics involved in filament formation/rupture, the filament size and correspondent current capabilities. The results reported in this thesis provide insight into a number of issues namely: (i) The fundamental limitations on the speed of operation of a bi-layer resistive memory are the time and voltage dependences of the switch-on mechanism. (ii) The results explain the wide spread in switching times reported in the literature and the apparently anomalous behaviour of the high conductance state namely the disappearance of the negative differential resistance region at high voltage scan rates which is commonly attributed to a “dead time” phenomenon which had remained elusive since it was first reported in the ‘60s. (iii) Assuming that the current is filamentary, Comsol simulations were performed and used to explain the observed dynamic properties of the current-voltage characteristics. Furthermore, the simulations suggest that filaments can interact with each other. (iv) The current-voltage characteristics have been studied as a function of temperature. The findings indicate that creation and annihilation of filaments is controlled by filling and neutralizing traps localized at the oxide/polymer interface. (v) Resistive switching was also studied in small-molecule OLEDs. It was shown that the degradation that leads to a loss of light output during operation is caused by the presence of a resistive switching layer. A diagnostic tool that predicts premature failure of OLEDs was devised and proposed. Resistive switching is a property of oxides. These layers can grow in a number of devices including, organic light emitting diodes (OLEDs), spin-valve transistors and photovoltaic devices fabricated in different types of material. Under strong electric fields the oxides can undergo dielectric breakdown and become resistive switching layers. Resistive switching strongly modifies the charge injection causing a number of deleterious effects and eventually device failure. In this respect the findings in this thesis are relevant to understand reliability issues in devices across a very broad field.

Interaction between glucocorticoid and adenosine A2A receptors in the hippocampus : implications for learning and memory

Tese de doutoramento, Ciências Biomédicas (Neurociências), Universidade de Lisboa, Faculdade de Medicina, 2014

A memória do testemunho e a influência das emoções na recolha e preservação da prova

Tese de doutoramento, Ciências e Tecnologias da Saúde (Desenvolvimento Humano e Social), Universidade de Lisboa, Faculdade de Medicina, 2015

Our Past Betrays Us: Collective Memory, Homicide and Southern Lynching

Thesis (Master's)--University of Washington, 2013

'The Rich Harmonics of Past Time': Memory and Montage

This article examines John Sommerfield’s 1936 novel, May Day, a work that experiments with multiple perspectives, voices and modes. The article examines the formal experiments of the novel in order to bring into focus contemporary debates around the aesthetics of socialist realism, the politics of Popular Front anti-fascism and the relationship between writers on the left and the legacies of literary modernism. The article suggests that while leftist writers’ appropriations of modernist techniques have been noted by critics, there has been a tendency to assume that such approaches were in contravention of the aesthetics of socialist realism. Socialist realism is shown to be more a fluid and disputed concept than such readings suppose, and Sommerfield’s adaptations of modernist textual strategies are interpreted as key components of a political aesthetic directed towards the problems of alienation and social fragmentation.

Effects of early life permethrin exposure on spatial working memory and on monoamine levels in different brain areas of pre-senescent rats

Pesticide exposure during brain development could represent an important risk factor for the onset of neurodegenerative diseases. Previous studies investigated the effect of permethrin (PERM) administered at 34 mg/kg, a dose close to the no observable adverse effect level (NOAEL) from post natal day (PND) 6 to PND 21 in rats. Despite the PERM dose did not elicited overt signs of toxicity (i.e. normal body weight gain curve), it was able to induce striatal neurodegeneration (dopamine and Nurr1 reduction, and lipid peroxidation increase). The present study was designed to characterize the cognitive deficits in the current animal model. When during late adulthood PERM treated rats were tested for spatial working memory performances in a T-maze-rewarded alternation task they took longer to choose for the correct arm in comparison to age matched controls. No differences between groups were found in anxiety-like state, locomotor activity, feeding behavior and spatial orientation task. Our findings showing a selective effect of PERM treatment on the T-maze task point to an involvement of frontal cortico-striatal circuitry rather than to a role for the hippocampus. The predominant disturbances concern the dopamine (DA) depletion in the striatum and, the serotonin (5-HT) and noradrenaline (NE) unbalance together with a hypometabolic state in the medial prefrontal cortex area. In the hippocampus, an increase of NE and a decrease of DA were observed in PERM treated rats as compared to controls. The concentration of the most representative marker for pyrethroid exposure (3-phenoxybenzoic acid) measured in the urine of rodents 12 h after the last treatment was 41.50 µ/L and it was completely eliminated after 96 h.

Software transactional memory as a building block for parallel embedded realtime systems

The recent trends of chip architectures with higher number of heterogeneous cores, and non-uniform memory/non-coherent caches, brings renewed attention to the use of Software Transactional Memory (STM) as a fundamental building block for developing parallel applications. Nevertheless, although STM promises to ease concurrent and parallel software development, it relies on the possibility of aborting conflicting transactions to maintain data consistency, which impacts on the responsiveness and timing guarantees required by embedded real-time systems. In these systems, contention delays must be (efficiently) limited so that the response times of tasks executing transactions are upper-bounded and task sets can be feasibly scheduled. In this paper we assess the use of STM in the development of embedded real-time software, defending that the amount of contention can be reduced if read-only transactions access recent consistent data snapshots, progressing in a wait-free manner. We show how the required number of versions of a shared object can be calculated for a set of tasks. We also outline an algorithm to manage conflicts between update transactions that prevents starvation.

WCET analysis considering contention on memory bus in COTS-based multicores

The usage of COTS-based multicores is becoming widespread in the field of embedded systems. Providing realtime guarantees at design-time is a pre-requisite to deploy real-time systems on these multicores. This necessitates the consideration of the impact of the contention due to shared low-level hardware resources on the Worst-Case Execution Time (WCET) of the tasks. As a step towards this aim, this paper first identifies the different factors that make the WCET analysis a challenging problem in a typical COTS-based multicore system. Then, we propose and prove, a mathematically correct method to determine tight upper bounds on the WCET of the tasks, when they are co-scheduled on different cores.

Response time analysis of COTS-Based multicores considering the contention on the shared memory bus

The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task.

Finding an upper bound on the increase in execution time due to contention on the memory bus in COTS-based multicore systems

Contention on the memory bus in COTS based multicore systems is becoming a major determining factor of the execution time of a task. Analyzing this extra execution time is non-trivial because (i) bus arbitration protocols in such systems are often undocumented and (ii) the times when the memory bus is requested to be used are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. We present a method for finding an upper bound on the extra execution time of a task due to contention on the memory bus in COTS based multicore systems. This method makes no assumptions on the bus arbitration protocol (other than assuming that it is work-conserving).