A framework for transforming, analyzing, and realizing software designs in unified modeling language

Unified Modeling Language (UML) is the most comprehensive and widely accepted object-oriented modeling language due to its multi-paradigm modeling capabilities and easy to use graphical notations, with strong international organizational support and industrial production quality tool support. However, there is a lack of precise definition of the semantics of individual UML notations as well as the relationships among multiple UML models, which often introduces incomplete and inconsistent problems for software designs in UML, especially for complex systems. Furthermore, there is a lack of methodologies to ensure a correct implementation from a given UML design. The purpose of this investigation is to verify and validate software designs in UML, and to provide dependability assurance for the realization of a UML design.^ In my research, an approach is proposed to transform UML diagrams into a semantic domain, which is a formal component-based framework. The framework I proposed consists of components and interactions through message passing, which are modeled by two-layer algebraic high-level nets and transformation rules respectively. In the transformation approach, class diagrams, state machine diagrams and activity diagrams are transformed into component models, and transformation rules are extracted from interaction diagrams. By applying transformation rules to component models, a (sub)system model of one or more scenarios can be constructed. Various techniques such as model checking, Petri net analysis techniques can be adopted to check if UML designs are complete or consistent. A new component called property parser was developed and merged into the tool SAM Parser, which realize (sub)system models automatically. The property parser generates and weaves runtime monitoring code into system implementations automatically for dependability assurance. The framework in the investigation is creative and flexible since it not only can be explored to verify and validate UML designs, but also provides an approach to build models for various scenarios. As a result of my research, several kinds of previous ignored behavioral inconsistencies can be detected.^

Internet Protocol Television (IPTV) controller realization with Very Large Scale Integration (VLSI) modules

Internet Protocol Television (IPTV) is a system where a digital television service is delivered by using Internet Protocol over a network infrastructure. There is considerable confusion and concern about the IPTV, since two different technologies have to be mended together to provide the end customers with some thing better than the conventional television. In this research, functional architecture of the IPTV system was investigated. Very Large Scale Integration based system for streaming server controller were designed and different ways of hosting a web server which can be used to send the control signals to the streaming server controller were studied. The web server accepts inputs from the keyboard and FPGA board switches and depending on the preset configuration the server will open a selected web page and also sends the control signals to the streaming server controller. It was observed that the applications run faster on PowerPC since it is embedded into the FPGA. Commercial market and Global deployment of IPTV were discussed.

Effective reconfigurable antenna designs to enhance performance and enable wireless powering

With the increase in traffic on the internet, there is a greater demand for wireless mobile and ubiquitous applications. These applications need antennas that are not only broadband, but can also work in different frequency spectrums. Even though there is a greater demand for such applications, it is still imperative to conserve power. Thus, there is a need to design multi-broadband antennas that do not use a lot of power. Reconfigurable antennas can work in different frequency spectrums as well as conserve power. The current designs of reconfigurable antennas work only in one band. There is a need to design reconfigurable antennas that work in different frequency spectrums. In this current era of high power consumption there is also a greater demand for wireless powering. This dissertation explores ideal designs of reconfigurable antennas that can improve performance and enable wireless powering. This dissertation also presents lab results of the multi-broadband reconfigurable antenna that was created. A detailed mathematical analyses, as well as extensive simulation results are also presented. The novel reconfigurable antenna designs can be extended to Multiple Input Multiple Output (MIMO) environments and military applications.^

Design and development of a one-degree-of-freedom force-reflecting manual controller prototype for teleoperation

The present research is carried out from the viewpoint of primarily space applications where human lives may be in danger if they are to work under these conditions. This work proposes to develop a one-degree-of-freedom (1-DOF) force-reflecting manual controller (FRMC) prototype for teleoperation, and address the effects of time delays commonly found in space applications where the control is accomplished via the earth-based control stations. To test the FRMC, a mobile robot (PPRK) and a slider-bar were developed and integrated to the 1-DOF FRMC. The software developed in Visual Basic is able to telecontrol any platform that uses an SV203 controller through the internet and it allows the remote system to send feedback information which may be in the form of visual or force signals. Time delay experiments were conducted on the platform and the effects of time delay on the FRMC system operation have been studied and delineated.

Design and construction of a portable force-reflecting manual controller for teleoperation systems

A man-machine system called teleoperator system has been developed to work in hazardous environments such as nuclear reactor plants. Force reflection is a type of force feedback in which forces experienced by the remote manipulator are fed back to the manual controller. In a force-reflecting teleoperation system, the operator uses the manual controller to direct the remote manipulator and receives visual information from a video image and/or graphical animation on the computer screen. This thesis presents the design of a portable Force-Reflecting Manual Controller (FRMC) for the teleoperation of tasks such as hazardous material handling, waste cleanup, and space-related operations. The work consists of the design and construction of a prototype 1-Degree-of-Freedom (DOF) FRMC, the development of the Graphical User Interface (GUI), and system integration. Two control strategies - PID and fuzzy logic controllers are developed and experimentally tested. The system response of each is analyzed and evaluated. In addition, the concept of a telesensation system is introduced, and a variety of design alternatives of a 3-DOF FRMC are proposed for future development.

Effective Reconfigurable Antenna Designs to Enhance Performance and Enable Wireless Powering

With the increase in traffic on the internet, there is a greater demand for wireless mobile and ubiquitous applications. These applications need antennas that are not only broadband, but can also work in different frequency spectrums. Even though there is a greater demand for such applications, it is still imperative to conserve power. Thus, there is a need to design multi-broadband antennas that do not use a lot of power. Reconfigurable antennas can work in different frequency spectrums as well as conserve power. The current designs of reconfigurable antennas work only in one band. There is a need to design reconfigurable antennas that work in different frequency spectrums. In this current era of high power consumption there is also a greater demand for wireless powering. This dissertation explores ideal designs of reconfigurable antennas that can improve performance and enable wireless powering. This dissertation also presents lab results of the multi-broadband reconfigurable antenna that was created. A detailed mathematical analyses, as well as extensive simulation results are also presented. The novel reconfigurable antenna designs can be extended to Multiple Input Multiple Output (MIMO) environments and military applications.

Equitably coloured balanced incomplete block designs

In this thesis we determine necessary and sufficient conditions for the existence of an equitably ℓ-colourable balanced incomplete block design for any positive integer ℓ > 2. In particular, we present a method for constructing non-trivial equitably ℓ-colourable BIBDs and prove that these designs are the only non-trivial equitably ℓ-colourable BIBDs that exist. We also observe that every equitable ℓ-colouring of a BIBD yields both an equalised ℓ-colouring and a proper 2-colouring of the same BIBD. We also discuss generalisations of these concepts including open questions for further research. The main results presented in this thesis also appear in [7].

A Comparison of Anchor-Item Designs for the Concurrent Calibration of Large Banks of Likert-Type Items

Current interest in measuring quality of life is generating interest in the construction of computerized adaptive tests (CATs) with Likert-type items. Calibration of an item bank for use in CAT requires collecting responses to a large number of candidate items. However, the number is usually too large to administer to each subject in the calibration sample. The concurrent anchor-item design solves this problem by splitting the items into separate subtests, with some common items across subtests; then administering each subtest to a different sample; and finally running estimation algorithms once on the aggregated data array, from which a substantial number of responses are then missing. Although the use of anchor-item designs is widespread, the consequences of several configuration decisions on the accuracy of parameter estimates have never been studied in the polytomous case. The present study addresses this question by simulation, comparing the outcomes of several alternatives on the configuration of the anchor-item design. The factors defining variants of the anchor-item design are (a) subtest size, (b) balance of common and unique items per subtest, (c) characteristics of the common items, and (d) criteria for the distribution of unique items across subtests. The results of this study indicate that maximizing accuracy in item parameter recovery requires subtests of the largest possible number of items and the smallest possible number of common items; the characteristics of the common items and the criterion for distribution of unique items do not affect accuracy.

Air traffic controller at Teterboro Airport, New Jersey

Inscriptions: Verso: [stamped] Photograph by Freda Leinwand. [463 West Street, Studio 229G, New York, NY 10014].

Air traffic controller at Teterboro Airport in New Jersey

Inscriptions: Verso: [stamped] Photograph by Freda Leinwand. [463 West Street, Studio 229G, New York, NY 10014].

Conceptual designs of multi-degree of freedom compliant parallel manipulators composed of wire-beam based compliant mechanisms

This paper proposes conceptual designs of multi-degree(s) of freedom (DOF) compliant parallel manipulators (CPMs) including 3-DOF translational CPMs and 6-DOF CPMs using a building block based pseudo-rigid-body-model (PRBM) approach. The proposed multi-DOF CPMs are composed of wire-beam based compliant mechanisms (WBBCMs) as distributed-compliance compliant building blocks (CBBs). Firstly, a comprehensive literature review for the design approaches of compliant mechanisms is conducted, and a building block based PRBM is then presented, which replaces the traditional kinematic sub-chain with an appropriate multi-DOF CBB. In order to obtain the decoupled 3-DOF translational CPMs (XYZ CPMs), two classes of kinematically decoupled 3-PPPR (P: prismatic joint, R: revolute joint) translational parallel mechanisms (TPMs) and 3-PPPRR TPMs are identified based on the type synthesis of rigid-body parallel mechanisms, and WBBCMs as the associated CBBs are further designed. Via replacing the traditional actuated P joint and the traditional passive PPR/PPRR sub-chain in each leg of the 3-DOF TPM with the counterpart CBBs (i.e. WBBCMs), a number of decoupled XYZ CPMs are obtained by appropriate arrangements. In order to obtain the decoupled 6-DOF CPMs, an orthogonally-arranged decoupled 6-PSS (S: spherical joint) parallel mechanism is first identified, and then two example 6-DOF CPMs are proposed by the building block based PRBM method. It is shown that, among these designs, two types of monolithic XYZ CPM designs with extended life have been presented.

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

Controller Time and Delay Costs - a Trade-off Analysis

Air traffic controller shortages remain a significant challenge in European ATM. Comparing different rules, we quantify the cost effectiveness of adding controller hours to Area Control Centre regulations to avert the delay cost impact on airlines. Typically, adding controller hours results in a net benefit. Distributions of delay duration and aircraft weight play an important role in determining the total cost of a regulation. Errors are likely to be incurred when analysing performance based on average delay values, particularly at the disaggregate level.