990 resultados para asymmetric power arch
Resumo:
Present day power systems are growing in size and complexity of operation with inter connections to neighboring systems, introduction of large generating units, EHV 400/765 kV AC transmission systems, HVDC systems and more sophisticated control devices such as FACTS. For planning and operational studies, it requires suitable modeling of all components in the power system, as the number of HVDC systems and FACTS devices of different type are incorporated in the system. This paper presents reactive power optimization with three objectives to minimize the sum of the squares of the voltage deviations (ve) of the load buses, minimization of sum of squares of voltage stability L-indices of load buses (¿L2), and also the system real power loss (Ploss) minimization. The proposed methods have been tested on typical sample system. Results for Indian 96-bus equivalent system including HVDC terminal and UPFC under normal and contingency conditions are presented.
Resumo:
A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.
Resumo:
In this paper, we propose power management algorithms for maximizing the utility of energy harvesting sensors (EHS) that operate purely on the basis of energy harvested from the environment. In particular, we consider communication (i.e., transmission and reception) power management issues for EHS under an energy neutrality constraint. We also consider the fixed power loss effects of the circuitry, the battery inefficiency and its storage capacity, in the design of the algorithms. We propose a two-stage structure that exploits the inherent difference in the timescales at which the energy harvesting and channel fading processes evolve, without loss of optimality of the resulting solution. The outer stage schedules the power that can be used by an inner stage algorithm, so as to maximize the long term average utility and at the same time maintain energy neutrality. The inner stage optimizes the communication parameters to achieve maximum utility in the short-term, subject to the power constraint imposed by the outer stage. We optimize the algorithms for different transmission schemes such as the truncated channel inversion and retransmission strategies. The performance of the algorithms is illustrated via simulations using solar irradiance data, and for the case of Rayleigh fading channels. The results demonstrate the significant performance benefits that can be obtained using the proposed power management algorithms compared to the energy efficient (optimum when there is no storage) and the uniform power consumption (optimum when the battery has infinite capacity and is perfectly efficient) approaches.
Resumo:
We have fabricated nano-Schottky diodes of CdTe QDs with platinum metal electrodes in metal-semiconductor-metal planar configuration by drop-casting. The observed high value of ideality factor (13.3) of the diode was possibly due to the presence of defects in colloidal QDs. We observed asymmetry and non-linear nature of I-V characteristics between forward and reverse directions, which has been explained in terms of size distributions of quantum dots due to coffee ring effect. Copyright 2011 Author(s). This article is distributed under a Creative Commons Attribution 3.0 Unported License. doi:10.1063/1.3669408]
Changing resonator geometry to boost sound power decouples size and song frequency in a small insect
Resumo:
Despite their small size, some insects, such as crickets, can produce high amplitude mating songs by rubbing their wings together. By exploiting structural resonance for sound radiation, crickets broadcast species-specific songs at a sharply tuned frequency. Such songs enhance the range of signal transmission, contain information about the signaler's quality, and allow mate choice. The production of pure tones requires elaborate structural mechanisms that control and sustain resonance at the species-specific frequency. Tree crickets differ sharply from this scheme. Although they use a resonant system to produce sound, tree crickets can produce high amplitude songs at different frequencies, varying by as much as an octave. Based on an investigation of the driving mechanism and the resonant system, using laser Doppler vibrometry and finite element modeling, we show that it is the distinctive geometry of the crickets' forewings (the resonant system) that is responsible for their capacity to vary frequency. The long, enlarged wings enable the production of high amplitude songs; however, as a mechanical consequence of the high aspect ratio, the resonant structures have multiple resonant modes that are similar in frequency. The drive produced by the singing apparatus cannot, therefore, be locked to a single frequency, and different resonant modes can easily be engaged, allowing individual males to vary the carrier frequency of their songs. Such flexibility in sound production, decoupling body size and song frequency, has important implications for conventional views of mate choice, and offers inspiration for the design of miniature, multifrequency, resonant acoustic radiators.
Resumo:
We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).
Resumo:
We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).