Inverse Class E amplifier and oscillator phase noise characteristics

This paper gives the first experimental characterisation of the phase noise response of the recently introduced Inverse Class E topology when operated as an amplifier and then as an oscillator. The results indicate that in amplifier and oscillator modes of operation conversion efficiencies of 64%, and 42% respectively are available, and that the excess PM noise added as a consequence of saturated Class E operation results in about a 10 dB increase in PM over that expected from a small-signal Class A amplifier operating at much lower efficiency. Inverse Class E phase transfer dependence on device drain bias and flicker noise are presented in order to show, respectively, that the Inverse Class E amplifier and oscillator follow the trends predicted by conventional phase noise theory. © 2007 EuMA.

Balanced class e amplifier based multimode modulator

In this paper we present an adaptation to the classical I/Q modulator topology which simultaneously allows it to operate both as a multi-modulation standard modulator, and as a high efficiency balanced amplifier. This is made possible by concurrently exploiting the ability of the Class E amplifiers to produce variable output power at maximum power added efficiency, PAE, by simple dc bias control while faithfully reproducing phase encoded signals. Experimental evidence for the behaviour of the modulator when operated in QPSK mode at 2.33 GHz with a 1 Msymbol/s rate shows that Error Vector Magnitude of less than 5% with amplifier PAE of 65% is possible. The multimode modulator presented here should lead to significantly reduced complexity, enhanced functionality transceivers for use in dc power sensitive handheld wireless applications. © 2007 EuMA.

Even order harmonic Series-L/Parallel-Tuned Class-E frequency multiplier

In this brief, we propose a new Class-E frequency multiplier based on the recently introduced Series-L/Parallel-Tuned Class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.

Transmission line matching effects on the performance of shunt-C/series-tuned and series-L/parallel-tuned Class-E amplifiers

The impact that the transmission-line load-network has on the performance of the recently introduced series-L/parallel-tuned Class-E amplifier and the classic shunt-C/series-tuned configuration when compared to optimally derived lumped load networks is discussed. In addition an improved load topology which facilitates harmonic suppression of up to 5 order as required for maximum Class-E efficiency as well as load resistance transformation and a design procedure involving the use of Kuroda's identity and Richard's transformation enable a distributed synthesis process which dispenses with the need for iterative tuning as previously required in order to achieve optimum Class-E operation. © 2005 IEEE.

Periodically loaded 1-D metallodielectric electromagnetic bandgap structures for miniaturisation and bandwidth enhancement

Periodic loading of 1-D metallodielectric electromagnetic bandgap (MEBG) structures has been rigorously investigated. Miniaturised and broadband MEBG structures have been produced by means of periodically loading a dipole array. A study has been carried out with regard to the loading mechanism, the number of stubs, the topology of the structure and the order of loading. Simulations have been carried out using a method of moments based software. First order uniform loading stubs have yielded a significant size reduction of the MEBG array and the bandwidth has doubled. Good agreement between simulations and measurements has been achieved. The current distribution on the proposed structure has been studied, yielding valuable insight. An interdigital topology has resulted in further miniaturisation and bandwidth enhancement. Fractal-type arrays have been produced after applying second order loading. A maximum miniaturisation of 2.5:1 has been achieved.

THEORY AND DESIGN OF A TUNABLE QUASI-LUMPED QUADRATURE COUPLER

In this article, we present the theory and a design methodology for a unable Quasi-Lumped Quadrature Coupler (QLQC). Because of its topology, the coupler is simply reconfigured by switching the bias of two varactor diodes via a very simple DC bias circuitry. No additional capacitors or inductors are required. A prototype at 3.5 GHz is etched on a 0.130-mm-thick layer substrate with a dielectric material of relative permittivity of 2.22. The simulated and measured scattering parameters are, presented. (c) 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2219-2222 2009: Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24526

A Novel Quad-Polarization Agile Patch Antenna

In this communication we present a novel polarization-agile microstrip antenna design. To dynamically change the polarization state, the radiating patch is fed by a tunable quasi-lumped coupler. The whole structure can be dynamically altered to radiate electromagnetic waves with vertical linear, horizontal linear, right-handed circular or left-handed circular polarization simply by changing the operating mode of the quasi-lumped coupler. Due to its topology the coupler is simply reconfigured by switching the bias of two varactor diodes via a very simple DC bias circuitry: no additional capacitors or inductors are required. A prototype is fabricated with a 0.762-mm-thick upper layer substrate for the radiating element and a 0.130-mm-thick layer substrate for the coupler circuit, both with the same dielectric material relative permittivity of 2.22. The simulated and measured scattering parameters, the axial ratio in circular radiation-mode and the cross-polarization level in linear mode, the gain and the radiation patterns are presented. The agile polarization capabilities of this new antenna, as demonstrated in this communication, underscore its suitability for modern wireless communications in a multi-path propagation environment.

Power combining techniques into unbalanced loads for Class-E and inverse Class-E amplifiers

A power combining strategy for Class-E and inverse Class-E amplifiers operating at high frequencies such that they can operate into unbalanced loads is proposed. This power combining method is particularly important for the inverse Class-E amplifier configuration whose single-stage topology is naturally limited for small-to-medium power applications. Design examples for the power combining synthesis of classical Class-E and then inverse Class-E amplifiers with specification 3 V-1.5 W-2.5 GHz are given. For this specification, it is shown that a three-branch combiner has a natural 50 V output impedance. The resulting circuits are simulated within Agilent Advanced Design Systems environment with good agreement to theoretical prediction. Further the performance of the proposed circuits when operated in a Linear amplification using Nonlinear Components transmitter configuration whereby two-branch amplifiers are driven with constant amplitude conjugate input phase signals is investigated.

Series-L/parallel-tuned comparison with shunt-C/series-tuned class-E power amplifier

An analysis of the operation of a series-L/parallel-tuned class-E amplifier and its equivalence to the classic shunt-C/series-tuned class-E amplifier are presented. The first reported closed form design equations for the series-L/parallel-tuned topology operating under ideal switching conditions are given. Furthermore, a design procedure is introduced that allows the effect that nonzero switch resistance has on amplifier performance efficiency to be accounted for. The technique developed allows optimal circuit components to be found for a given device series resistance. For a relatively high value of switching device ON series resistance of 4O, drain efficiency of around 66% for the series-L/parallel-tuned topology, and 73% for the shunt-C/series-tuned topology appear to be the theoretical limits. At lower switching device series resistance levels, the efficiency performance of each type are similar, but the series-L/parallel-tuned topology offers some advantages in terms of its potential for MMIC realisation. Theoretical analysis is confirmed by numerical simulation for a 500mW (27dBm), 10% bandwidth, 5 V series-L/parallel-tuned, then, shunt-C/series-tuned class E power amplifier, operating at 2.5 GHz, and excellent agreement between theory and simulation results is achieved. The theoretical work presented in the paper should facilitate the design of high-efficiency switched amplifiers at frequencies commensurate with the needs of modern mobile wireless applications in the microwave frequency range, where intrinsically low-output-capacitance MMIC switching devices such as pHEMTs are to be used.

Two-dimensional Banach spaces with polynomial numerical index zero

We study two-dimensional Banach spaces with polynomial numerical indices equal to zero.

A hierarchical multiclass support vector machine incorporated with holistic triple learning units

This paper proposes a new hierarchical learning structure, namely the holistic triple learning (HTL), for extending the binary support vector machine (SVM) to multi-classification problems. For an N-class problem, a HTL constructs a decision tree up to a depth of A leaf node of the decision tree is allowed to be placed with a holistic triple learning unit whose generalisation abilities are assessed and approved. Meanwhile, the remaining nodes in the decision tree each accommodate a standard binary SVM classifier. The holistic triple classifier is a regression model trained on three classes, whose training algorithm is originated from a recently proposed implementation technique, namely the least-squares support vector machine (LS-SVM). A major novelty with the holistic triple classifier is the reduced number of support vectors in the solution. For the resultant HTL-SVM, an upper bound of the generalisation error can be obtained. The time complexity of training the HTL-SVM is analysed, and is shown to be comparable to that of training the one-versus-one (1-vs.-1) SVM, particularly on small-scale datasets. Empirical studies show that the proposed HTL-SVM achieves competitive classification accuracy with a reduced number of support vectors compared to the popular 1-vs-1 alternative.

A heuristic model for the simulation of the deformation of elastic and spongy material for virtual reality applications

This paper presents a practical algorithm for the simulation of interactive deformation in a 3D polygonal mesh model. The algorithm combines the conventional simulation of deformation using a spring-mass-damping model, solved by explicit numerical integration, with a set of heuristics to describe certain features of the transient behaviour, to increase the speed and stability of solution. In particular, this algorithm was designed to be used in the simulation of synthetic environments where it is necessary to model realistically, in real time, the effect on non-rigid surfaces being touched, pushed, pulled or squashed. Such objects can be solid or hollow, and have plastic, elastic or fabric-like properties. The algorithm is presented in an integrated form including collision detection and adaptive refinement so that it may be used in a self-contained way as part of a simulation loop to include human interface devices that capture data and render a realistic stereoscopic image in real time. The algorithm is designed to be used with polygonal mesh models representing complex topology, such as the human anatomy in a virtual-surgery training simulator. The paper evaluates the model behaviour qualitatively and then concludes with some examples of the use of the algorithm.

On the derived category of a regular toric scheme

Let X be a quasi-compact scheme, equipped with an open covering by affine schemes U s = Spec A s . A quasi-coherent sheaf on X gives rise, by taking sections over the U s , to a diagram of modules over the coordinate rings A s , indexed by the intersection poset S of the covering. If X is a regular toric scheme over an arbitrary commutative ring, we prove that the unbounded derived category of quasi-coherent sheaves on X can be obtained from a category of Sop-diagrams of chain complexes of modules by inverting maps which induce homology isomorphisms on hyper-derived inverse limits. Moreover, we show that there is a finite set of weak generators, one for each cone in the fan S. The approach taken uses the machinery of Bousfield–Hirschhorn colocalisation of model categories. The first step is to characterise colocal objects; these turn out to be homotopy sheaves in the sense that chain complexes over different open sets U s agree on intersections up to quasi-isomorphism. In a second step it is shown that the homotopy category of homotopy sheaves is equivalent to the derived category of X.