Integrated optics � technology and applications

The emergence of optoelectronics and photonics as viable alternatives to electronics in many key areas of engineering relevance is indeed significant. This paper presents a tutorial review of integrated optics � a technologically important development in photonics. Materials, processes, device technology and applications are highlighted.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

The physics and technology of gallium antimonide: An emerging optoelectronic material

Recent advances in nonsilica fiber technology have prompted the development of suitable materials for devices operating beyond 1.55 mu m. The III-V ternaries and quaternaries (AlGaIn)(AsSb) lattice matched to GaSb seem to be the obvious choice and have turned out to be promising candidates for high speed electronic and long wavelength photonic devices. Consequently, there has been tremendous upthrust in research activities of GaSb-based systems. As a matter of fact, this compound has proved to be an interesting material for both basic and applied research. At present, GaSb technology is in its infancy and considerable research has to be carried out before it can be employed for large scale device fabrication. This article presents an up to date comprehensive account of research carried out hitherto. It explores in detail the material aspects of GaSb starting from crystal growth in bulk and epitaxial form, post growth material processing to device feasibility. An overview of the lattice, electronic, transport, optical and device related properties is presented. Some of the current areas of research and development have been critically reviewed and their significance for both understanding the basic physics as well as for device applications are addressed. These include the role of defects and impurities on the structural, optical and electrical properties of the material, various techniques employed for surface and bulk defect passivation and their effect on the device characteristics, development of novel device structures, etc. Several avenues where further work is required in order to upgrade this III-V compound for optoelectronic devices are listed. It is concluded that the present day knowledge in this material system is sufficient to understand the basic properties and what should be more vigorously pursued is their implementation for device fabrication. (C) 1997 American Institute of Physics.

Combinatorial logic synthesis using technology directed decomposition

The aim of logic synthesis is to produce circuits which satisfy the given boolean function while meeting timing constraints and requiring the minimum silicon area. Logic synthesis involves two steps namely logic decomposition and technology mapping. Existing methods treat the two as separate operation. The traditional approach is to minimize the number of literals without considering the target technology during the decomposition phase. The decomposed expressions are then mapped on to the target technology to optimize the area, Timing optimization is carried out subsequently, A new approach which treats logic decomposition and technology maping as a single operation is presented. The logic decomposition is based on the parameters of the target technology. The area and timing optimization is carried out during logic decomposition phase itself. Results using MCNC circuits are presented to show that this method produces circuits which are 38% faster while requiring 14% increase in area.

Training Young Minds for Nanoscience and Technology: Issues and Challenges

This article explores issues and challenges in the field of education in nanoscience and technology with special emphasis with respect to India, where an expanding programme of research in nano science and technology is in place. The article does not concentrate on actual curricula that are needed in nano science and technology education course. Rather it focuses on the desirability of nanoscience and technology education at different levels of education and future prospect of students venturing into this within the economic and cultural milieu of India. We argue that care is needed in developing the education programme in India. However, the risk is worth taking as the education on nanoscience and technology can bridge the man power gap not only in this area of technology but also related technologies of hardware and micro electronics for which the country is a promising destination at global level. This will also unlock the demographical advantage that India will enjoy in the next five decades.

Role of Management Decision Variables in Determining Technology Progress and Technical Efficiency in Indian Electronic Industry

This paper analyses the influence of management on Technical Efficiency Change (TEC) and Technological Progress (TP) in the communication equipment and consumer electronics sub-sectors of Indian hardware electronics industry. Each sub-sector comprises 13 sample firms for two time periods.The primary objective is to determine the relative contribution of TP and TEC to TFP Growth (TFPG) and to establish the influence of firm specific operational management decision variables on these two components. The study finds that both the sub-sectors have strived and achieved steady TP but not TEC in the period of economic liberalisation to cope with the intensifying competition. The management decisions with respect to asset and profit utilization, vertical integration, among others, improved TP and TE in the sub-sectors. However, R&D investments and technology imports proved costly for TFP indicating inadequate efforts and/or poor resource utilisation by the management. Management was found to be complacent in terms of improving or developing their own technology as indicated by their higher dependence on import of raw materials and no influence of R&D on TP.

Necessity for quatum simulation for future technology nodes

In this paper we present and compare the results obtained from semi-classical and quantum mechanical simulation for a double gate MOSFET structure to analyze the electrostatics and carrier dynamics of this device. The geometries like gate length, body thickness of this device have been chosen according to the ITRS specification for the different technology nodes. We have shown the extent of deviation between the semi- classical and quantum mechanical results and hence the need of quantum simulations for the promising nanoscale devices in the future technology nodes predicted in ITRS.

Correlations between structure and thermodynamic properties of spinels and their applications in technology

Measurements a/the Gibbs' energy enthalpy and entrupy vffarmation oj chromites, vanadites and alumlnat.:s 0/ F", Ni. Co'. Mn, Zn Mg and Cd, using solid oxide galvanic cells over a ternperature range extending approximately lOOO°C, have shown that the '~'Ilir"!,,, J'JrIl/iJ~ tion 0/ cubic 2-3 oxide spinel phases (MX!O,), from component oxide (MO) with rock-salt and X.Os whir c(1f'l/!ldwn st!'llt'lw,·. call b,' represented by a semi-empirical correlalion, ~S~ = --LiS + L'i,SM +~S~:"d(±O.3) cal.deg-1 mol-1 where /',.SM Is the entropy 0/calian mixing oillhe tetrahedral alld octahedral sites o/the spinel and Sr:~ is tlie enfropy associaf,'d Wifh Ih,' randomization a/the lahn-Telier distortions. A review a/the methods/or evaluating the cation distriblltion lfl spille!s suggeJ{j' l/r,l! Ihe most promising scheme is based Oil octahedral site preference energies from the crystal field theory for the Iral1silioll IIIl'f"! IlIIL';. For I/""-Irallsifioll melal cal ions site preference energies are derived relative /0 thol'lt fLI, [ransilion metal ions from measured high tClllP('ftJi ure Cal iUlI disll iiJuriol1 in spine! phases thar contail! one IransilioJl metal and another non-transition metal carion. For 2-3 srinds compulatiorrs b,IS"J Oil i.!c[J;' Temkin mixing on each catioll subialtice predici JistributionJ that are In fair agreement with X-ray and 1I1'IIIrOll ditTraction, /IIdg""!ic dll.! electrical propcrries, and spectroscopic measurements. In 2-4 spineis mixing vI ions do not foliow strictly ideal slllIistli:al Jaws, Th,' OIl/up) associated with the randomizalion 0/the Jllhn-Teller dislOriioll" appear to be significant, only ill spinels witll 3d'. 3d', 3d' (ifld~UI' iOtls in tetrahedral and 3d' and 3d9 ions in octahedral positions. Application 0/this structural model for predicting the thermodynamic proputies ofspinel solid .,olutiofl5 or,' illustrated. F,lr complex systems additional contributions arising from strain fields, redox equilibria and off-center ions have to be qllalllififti. The entropy correlation for spinels provides a method for evaluating structure tran:.jormafiofl entropies in silllple o.\id.-s, ["founlllion on the relative stabilities ofoxides in different crystallCtructures is USe/III for computer ea/culaliof! a/phase dfugrullls ofIlIrer,',,1 III (N.lll1ie5 by method, similar to thost: used by Kaufman and Bernstein for refractory alloy systems. Examples oftechnoiogical appliCation tnclude the predictioll ofdeoxidation equilibria in Fe-Mn-AI-O s),slelll at 1600°C duj ,'Ulllpltfalion 0/phase relutions in Fe-Ni-Cr-S system,

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.