Elements of scalable data processing

Cooperating objects (COs) is a recently coined term used to signify the convergence of classical embedded computer systems, wireless sensor networks and robotics and control. We present essential elements of a reference architecture for scalable data processing for the CO paradigm.

Practices and trends of telework in the Portuguese industry: the results of surveys in the textile, metal and software sectors

The aim of the TeleRisk Project on labour relations and professional risks within the context of teleworking in Portugal – supported by IDICT – Institute for Development and Inspection of Working Conditions (Ministry of Labour), is to study the practices and forms of teleworking in the manufacturing sectors in Portugal. The project chose also the software industry as a reference sector, even though it does not intend to exclude from the study any other sector of activity or the so-called “hybrid” forms of work. However, the latter must have some of the characteristics of telework. The project thus takes into account the so-called “traditional” sectors of activity, namely textile and machinery and metal engineering (machinery and equipment), not usually associated to this type of work. However, telework could include, in the so-called “traditional” sectors, other variations that are not found in technologically based sectors. One of the evaluation methods for the dynamics associated to telework consisted in carrying out surveys by means of questionnaires, aimed at employers in the sectors analysed. This paper presents some of the results of those surveys. It is important to mention that, being a preliminary analysis, it means that it does not pretend to have exhausted all the issues in the survey, but has meant that it shows the bigger tendencies, in terms of teleworking practices, of the Portuguese industry.

Schedulability analysis of generalized multiframe traffic on multihop-networks comprising software-implemented ethernet switches

Consider a multihop network comprising Ethernet switches. The traffic is described with flows and each flow is characterized by its source node, its destination node, its route and parameters in the generalized multiframe model. Output queues on Ethernet switches are scheduled by static-priority scheduling and tasks executing on the processor in an Ethernet switch are scheduled by stride scheduling. We present schedulability analysis for this setting.

Traceability support in software product lines

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Informática.

Autonomic workflow activities: the award framework

Workflows have been successfully applied to express the decomposition of complex scientific applications. This has motivated many initiatives that have been developing scientific workflow tools. However the existing tools still lack adequate support to important aspects namely, decoupling the enactment engine from workflow tasks specification, decentralizing the control of workflow activities, and allowing their tasks to run autonomous in distributed infrastructures, for instance on Clouds. Furthermore many workflow tools only support the execution of Direct Acyclic Graphs (DAG) without the concept of iterations, where activities are executed millions of iterations during long periods of time and supporting dynamic workflow reconfigurations after certain iteration. We present the AWARD (Autonomic Workflow Activities Reconfigurable and Dynamic) model of computation, based on the Process Networks model, where the workflow activities (AWA) are autonomic processes with independent control that can run in parallel on distributed infrastructures, e. g. on Clouds. Each AWA executes a Task developed as a Java class that implements a generic interface allowing end-users to code their applications without concerns for low-level details. The data-driven coordination of AWA interactions is based on a shared tuple space that also enables support to dynamic workflow reconfiguration and monitoring of the execution of workflows. We describe how AWARD supports dynamic reconfiguration and discuss typical workflow reconfiguration scenarios. For evaluation we describe experimental results of AWARD workflow executions in several application scenarios, mapped to a small dedicated cluster and the Amazon (Elastic Computing EC2) Cloud.

Dpws middleware to support agent-based manufacturing control and simulation

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Enabling Global Experiments With Interactive Reconfiguration And Steering By Multiple Users

In global scientific experiments with collaborative scenarios involving multinational teams there are big challenges related to data access, namely data movements are precluded to other regions or Clouds due to the constraints on latency costs, data privacy and data ownership. Furthermore, each site is processing local data sets using specialized algorithms and producing intermediate results that are helpful as inputs to applications running on remote sites. This paper shows how to model such collaborative scenarios as a scientific workflow implemented with AWARD (Autonomic Workflow Activities Reconfigurable and Dynamic), a decentralized framework offering a feasible solution to run the workflow activities on distributed data centers in different regions without the need of large data movements. The AWARD workflow activities are independently monitored and dynamically reconfigured and steering by different users, namely by hot-swapping the algorithms to enhance the computation results or by changing the workflow structure to support feedback dependencies where an activity receives feedback output from a successor activity. A real implementation of one practical scenario and its execution on multiple data centers of the Amazon Cloud is presented including experimental results with steering by multiple users.

Intermodulation in active reconfigurable antennas

Due to the application of active components into antennas these became a source of distortion on wireless communication systems. In this paper we explore the nonlinear effects occurring in a frequency reconfigurable antenna operating with a PIN Diode. We describe the measurement setup used to check the antenna intermodulation products and the measured compression and third order intermodulation limitations of a frequency reconfigurable antenna, operating at the UMTS and WLAN frequencies.

Non-uniform microstrip antenna array for RX DSRC communications

The urgent need to mitigate traffic problems such as accidents, road hazards, pollution and traffic jam have strongly driven the development of vehicular communications. DSRC (Dedicated Short Range Communications) is the technology of choice in vehicular communications, enabling real time information exchange among vehicles V2V (Vehicle-to-Vehicle) and between vehicles and infrastructure V2I (Vehicle-Infrastructure). This paper presents a receiving antenna for a single lane DSRC control unit. The antenna is a non-uniform array with five microstrip patches. The obtained beam width, bandwidth and circular polarization quality, among other characteristics, are compatible with the DSRC standards, making this antenna suitable for this application. © 2014 IEEE.

Performance comparison of a VDFLL versus VDLL and scalar GNSS receiver architectures in Harsh scenarios

We analyze the advantages and drawbacks of a vector delay/frequency-locked loop (VDFLL) architecture regarding the conventional scalar and the vector delay-locked loop (VDLL) architectures for GNSS receivers in harsh scenarios that include ionospheric scintillation, multipath, and high dynamics motion. The VDFLL is constituted by a bank of code and frequency discriminators feeding a central extended Kaiman filter (EKF) that estimates the receiver's position, velocity, and clock bias. Both code and frequency loops are closed vectorially through the EKF. The VDLL closes the code loop vectorially and the phase loops through individual PLLs while the scalar receiver closes both loops by means of individual independent PLLs and DLLs.

SiC pinpin photonic for linking the visible spectrum to the telecom gap

Expanding far beyond traditional applications at telecommunications wavelengths, the SiC photonic devices has recently proven its merits for working with visible range optical signals. Reconfigurable wavelength selectors are essential sub-systems for implementing reconfigurable WDM networks and optical signal processing. Visible range to telecom band spectral translation in SiC/Si can be accomplished using wavelength selector under appropriated optical bias, acting as reconfigurable active filters. In this paper we present a monolithically integrated wavelength selector based on a multilayer SiC/Si integrated optical filters that requires optical switches to select wavelengths. The selector filter is realized by using double pin/pin a-SiC:H photodetector with front and back biased optical gating elements. Red, green, blue and violet communication channels are transmitted together, each one with a specific bit sequence. The combined optical signal is analyzed by reading out the generated photocurrent, under different background wavelengths applied either from the front or the back side. The backgrounds acts as channel selectors that selects one or more channels by splitting portions of the input multi-channel optical signals across the front and back photodiodes. The transfer characteristics effects due to changes in steady state light, irradiation side and frequency are presented. The relationship between the optical inputs and the digital output levels is established. (C) 2014 Elsevier B.V. All rights reserved.

Component-based software engineering: a quantitative approach

Dissertação apresentada para a obtenção do Grau de Doutor em Informática pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

The impact of different power dividers used in a non-uniform planar antenna array

Wireless communications are widely used for various applications, requiring antennas with different features. Often, to achieve the desired radiation pattern, is necessary to employ antenna arrays, using non-uniform excitation on its elements. Power dividers can be used and the best known are the T-junction and the Wilkinson power divider, whose main advantage is the isolation between output ports. In this paper the impact of this isolation on the overall performance of a circularly polarized planar antenna array using non-uniform excitation is investigated. Results show a huge decrease of the array bandwidths either in terms of return loss or in polarization, without resistors. © 2014 IEEE.

Trends Of CPU, GPU and FPGA for high-performance computing

Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM).

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.