Analysis and design of multirate synchronous sampling schemes for sparse multiband signals

We consider the problem of developing efficient sampling schemes for multiband sparse signals. Previous results on multicoset sampling implementations that lead to universal sampling patterns (which guarantee perfect reconstruction), are based on a set of appropriate interleaved analog to digital converters, all of them operating at the same sampling frequency. In this paper we propose an alternative multirate synchronous implementation of multicoset codes, that is, all the analog to digital converters in the sampling scheme operate at different sampling frequencies, without need of introducing any delay. The interleaving is achieved through the usage of different rates, whose sum is significantly lower than the Nyquist rate of the multiband signal. To obtain universal patterns the sampling matrix is formulated and analyzed. Appropriate choices of the parameters, that is the block length and the sampling rates, are also proposed.

Design of universal multicoset sampling patterns for compressed sensing of multiband sparse signals

Many problems in digital communications involve wideband radio signals. As the most recent example, the impressive advances in Cognitive Radio systems make even more necessary the development of sampling schemes for wideband radio signals with spectral holes. This is equivalent to considering a sparse multiband signal in the framework of Compressive Sampling theory. Starting from previous results on multicoset sampling and recent advances in compressive sampling, we analyze the matrix involved in the corresponding reconstruction equation and define a new method for the design of universal multicoset codes, that is, codes guaranteeing perfect reconstruction of the sparse multiband signal.

Structural health monitoring network system with wireless communications inside closed aerospace structures

Structural Health Monitoring (SHM) requires integrated "all in one" electronic devices capable of performing analysis of structural integrity and on-board damage detection in aircraft?s structures. PAMELA III (Phased Array Monitoring for Enhanced Life Assessment, version III) SHM embedded system is an example of this device type. This equipment is capable of generating excitation signals to be applied to an array of integrated piezoelectric Phased Array (PhA) transducers stuck to aircraft structure, acquiring the response signals, and carrying out the advanced signal processing to obtain SHM maps. PAMELA III is connected with a host computer in order to receive the configuration parameters and sending the obtained SHM maps, alarms and so on. This host can communicate with PAMELA III through an Ethernet interface. To avoid the use of wires where necessary, it is possible to add Wi-Fi capabilities to PAMELA III, connecting a Wi-Fi node working as a bridge, and to establish a wireless communication between PAMELA III and the host. However, in a real aircraft scenario, several PAMELA III devices must work together inside closed structures. In this situation, it is not possible for all PAMELA III devices to establish a wireless communication directly with the host, due to the signal attenuation caused by the different obstacles of the aircraft structure. To provide communication among all PAMELA III devices and the host, a wireless mesh network (WMN) system has been implemented inside a closed aluminum wingbox. In a WMN, as long as a node is connected to at least one other node, it will have full connectivity to the entire network because each mesh node forwards packets to other nodes in the network as required. Mesh protocols automatically determine the best route through the network and can dynamically reconfigure the network if a link drops out. The advantages and disadvantages on the use of a wireless mesh network system inside closed aerospace structures are discussed.

Integrated electronic system for ultrasonic structural health monitoring

A fully integrated on-board electronic system that can perform in-situ structural health monitoring (SHM) of aircraft?s structures using specifically designed equipment for SHM based on guided wave ultrasonic method or Lamb waves? method is introduced. This equipment is called Phased Array Monitoring for Enhanced Life Assessment (PAMELA III) and is an essential part of overall PAMELA SHM? system. PAMELA III can generate any kind of excitation signals, acquire the response signals that propagate throughout the structure being tested, and perform the signal processing for damage detection directly on the structure without need to send the huge amount of raw signals but only the final SHM maps. It monitors the structure by means of an array of integrated Phased Array (PhA) transducers preferably bonded onto the host structure. The PAMELA III hardware for SHM mapping has been designed, built and subjected to laboratory tests, using aluminum and CFRP structures. The 12 channel system has been designed to be low weight (265 grams only), to have a small form factor, to be directly mounted above the integrated PhA transducers without need for cables and to be EMI protected so that the equipment can be taken on board an aircraft to perform required SHM analyses by use of embedded SHM algorithms. Moreover, the autonomous, automatic and on real-time working procedure makes it suitable for the avionic field, sending the corresponding alerts, maps and reports to external equipment.

Traffic jam driving with NMV avoidance

n recent years, the development of advanced driver assistance systems (ADAS) ��� mainly based on lidar and cameras ��� has considerably improved the safety of driving in urban environments. These systems provide warning signals for the driver in the case that any unexpected traffic circumstance is detected. The next step is to develop systems capable not only of warning the driver but also of taking over control of the car to avoid a potential collision. In the present communication, a system capable of autonomously avoiding collisions in traffic jam situations is presented. First, a perception system was developed for urban situations���in which not only vehicles have to be considered, but also pedestrians and other non-motor-vehicles (NMV). It comprises a differential global positioning system (DGPS) and wireless communication for vehicle detection, and an ultrasound sensor for NMV detection. Then, the vehicle's actuators ��� brake and throttle pedals ��� were modified to permit autonomous control. Finally, a fuzzy logic controller was implemented capable of analyzing the information provided by the perception system and of sending control commands to the vehicle's actuators so as to avoid accidents. The feasibility of the integrated system was tested by mounting it in a commercial vehicle, with the results being encouraging.

MPEG-M: A Digital Media Ecosystem for Interoperable Applications

MPEG-M is a suite of ISO/IEC standards (ISO/IEC 23006) that has been developed under the auspices of Moving Picture Experts Group (MPEG). MPEG-M, also known as Multimedia Service Platform Technologies (MSPT), facilitates a collection of multimedia middleware APIs and elementary services as well as service aggregation so that service providers can offer users a plethora of innovative services by extending current IPTV technology toward the seamless integration of personal content creation and distribution, e-commerce, social networks and Internet distribution of digital media.

Implementation of wireless communication based on Software Defined Radio

In current communication systems, there are many new challenges like various competitive standards, the scarcity of frequency resource, etc., especially the development of personal wireless communication systems result the new system update faster than ever before, the conventional hardware-based wireless communication system is difficult to adapt to this situation. The emergence of SDR enabled the third revolution of wireless communication which from hardware to software and build a flexible, reliable, upgradable, reusable, reconfigurable and low cost platform. The Universal Software Radio Peripheral (USRP) products are commonly used with the GNU Radio software suite to create complex SDR systems. GNU Radio is a toolkit where digital signal processing blocks are written in C++, and connected to each other with Python. This makes it easy to develop more sophisticated signal processing systems, because many blocks already written by others and you can quickly put them together to create a complete system. Although the main function of GNU Radio is not be a simulator, but if there is no RF hardware components,it supports to researching the signal processing algorithm based on pre-stored and generated data by signal generator. This thesis introduced SDR platform from hardware (USRP) and software(GNU Radio), as well as some basic modulation techniques in wireless communication system. Based on the examples provided by GNU Radio, carried out some related experiments, for example GSM scanning and FM radio station receiving on USRP. And make a certain degree of improvement based on the experience of some investigators to observe OFDM spectrum and simulate real-time video transmission. GNU Radio combine with USRP hardware proved to be a valuable lab platform for implementing complex radio system prototypes in a short time. RESUMEN. Software Defined Radio (SDR) es una tecnolog��a emergente que est�� creando un impacto revolucionario en la tecnolog��a de radio convencional. Un buen ejemplo de radio software son los sistemas de c��digo abierto llamados GNU Radio que emplean un kit de herramientas de desarrollo de software libre. En este trabajo se ha empleado un kit de desarrollo comercial (Ettus Research) que consiste en un m��dulo de procesado de se��al y un hardaware sencillo. El m��dulo emplea un software de desarrollo basado en Linux sobre el que se pueden implementar aplicaciones de radio software muy variadas. El hardware de desarrollo consta de un microprocesador de prop��sito general, un dispositivo programable (FPGA) y un interfaz de radiofrecuencia que cubre de 50 a 2200MHz. Este hardware se conecta al PC por medio de un interfaz USB de 8Mb/s de velocidad. Sobre la plataforma de Ettus se pueden ejecutar aplicaciones GNU radio que utilizan principalmente lenguaje de programaci��n Python para implementarse. Sin embargo, su m��dulo de procesado de se��al est�� construido en C + + y emplea un microprocesador con aritm��tica de coma flotante. Por lo tanto, los desarrolladores pueden r��pida y f��cilmente construir aplicaciones en tiempo real sistemas de comunicaci��n inal��mbrica de alta capacidad. Aunque su funci��n principal no es ser un simulador, si no puesto que hay componentes de hardware RF, Radio GNU sirve de apoyo a la investigaci��n del algoritmo de procesado de se��ales basado en pre-almacenados y generados por los datos del generador de se��al. En este trabajo fin de m��ster se ha evaluado la plataforma de hardware de DEG (USRP) y el software (GNU Radio). Para ello se han empleado algunas t��cnicas de modulaci��n b��sicas en el sistema de comunicaci��n inal��mbrica. A partir de los ejemplos proporcionados por GNU Radio, hemos realizado algunos experimentos relacionados, por ejemplo, escaneado del espectro, demodulaci��n de se��ales de FM empleando siempre el hardware de USRP. Una vez evaluadas aplicaciones sencillas se ha pasado a realizar un cierto grado de mejora y optimizaci��n de aplicaciones complejas descritas en la literatura. Se han empleado aplicaciones como la que consiste en la generaci��n de un espectro de OFDM y la simulaci��n y transmisi��n de se��ales de v��deo en tiempo real. Con estos resultados se est�� ahora en disposici��n de abordar la elaboraci��n de aplicaciones complejas.

Integraci��n del descodificador OpenSVC en el DSP del OMAP3530

Hoy en d��a el uso de dispositivos port��tiles multimedia es ya una realidad totalmente habitual. Adem��s, estos dispositivos tienen una capacidad de c��lculo y unos recursos gr��ficos y de memoria altos, tanto es as�� que por ejemplo en un m��vil se pueden reproducir v��deos de muy alta calidad o tener capacidad para manejar entornos 3D. El precio del uso de estos recursos es un mayor consumo de bater��a que en ocasiones es demasiado alto y acortan en gran medida la vida de la carga ��til de la bater��a. El Grupo de Dise��o Electr��nico y Microelectr��nico de la Universidad Polit��cnica de Madrid ha abierto una l��nea de trabajo que busca la optimizaci��n del consumo de energ��a en este tipo de dispositivos, concretamente en el ��mbito de la reproducci��n de v��deo. El enfoque para afrontar la soluci��n del problema se basa en obtener un mayor rendimiento de la bater��a a costa de disminuir la experiencia multimedia del usuario. De esta manera, cuando la carga de la bater��a est�� por debajo de un determinado umbral mientras el dispositivo est�� reproduciendo un v��deo de alta calidad ser�� el dispositivo quien se autoconfigure din��micamente para consumir menos potencia en esta tarea, reduciendo la tasa de im��genes por segundo o la resoluci��n del v��deo que se descodifica. Adem��s de lo citado anteriormente se propone dividir la descodificaci��n y la representaci��n del v��deo en dos procesadores, uno de prop��sito general y otro para procesado digital de se��al, con esto se consigue que tener la misma capacidad de c��lculo que con un solo procesador pero a una frecuencia menor. Para materializar la propuesta se usar�� la tarjeta BeagleBoard basada en un procesador multin��cleo OMAP3530 de Texas Instrument que contiene dos n��cleos: un ARM1 Cortex-A8 y un DSP2 de la familia C6000. Este procesador multin��cleo adem��s permite modificar la frecuencia de reloj y la tensi��n de alimentaci��n din��micamente para conseguir reducir de este modo el consumo del terminal. Por otro lado, como reproductor de v��deos se utilizar�� una versi��n de MPlayer que integra un descodificador de v��deo escalable que permite elegir din��micamente la resoluci��n o las im��genes por segundo que se decodifican para posteriormente mostrarlas. Este reproductor se ejecutar�� en el n��cleo ARM pero debido a la alta carga computacional de la descodificaci��n de v��deos, y que el ARM no est�� optimizado para este tipo de procesado de datos, el reproductor debe encargar la tarea de la descodificaci��n al DSP. El objetivo de este Proyecto Fin de Carrera consiste en que mientras el descodificador de v��deo est�� ejecut��ndose en el n��cleo DSP y el Mplayer en el n��cleo ARM del OMAP3530 se pueda elegir din��micamente qu�� parte del v��deo se descodifica, es decir, seleccionar en tiempo real la calidad o capa del v��deo que se quiere mostrar. Haciendo esto, se podr�� quitar carga computacional al n��cleo ARM y asign��rsela al DSP el cu��l puede procesarla a menor frecuencia para ahorrar bater��a. 1 ARM: Es una arquitectura de procesadores de prop��sito general basada en RISC (Reduced Instruction Set Computer). Es desarrollada por la empresa inglesa ARM holdings. 2 DSP: Procesador Digital de Se��al (Digital Signal Processor). Es un sistema basado en procesador, el cual est�� orientado al c��lculo matem��tico a altas velocidad. Generalmente poseen varias unidades aritm��tico-l��gicas (ALUs) para conseguir realizar varias operaciones simult��neamente. SUMMARY. Nowadays, the use of multimedia devices is a well known reality. In addition, these devices have high graphics and calculus performance and a lot of memory as well. In instance, we can play high quality videos and 3D environments in a mobile phone. That kind of use may increase the device's power consumption and make shorter the battery duration. Electronic and Microelectronic Design Group of Technical University of Madrid has a research line which is looking for optimization of power consumption while these devices are playing videos. The solution of this trouble is based on taking more advantage of battery by decreasing multimedia user experience. On this way, when battery charge is under a threshold while device is playing a high quality video the device is going to configure itself dynamically in order to decrease its power consumption by decreasing frame per second rate, video resolution or increasing the noise in the decoded frame. It is proposed splitting decoding and representation tasks in two processors in order to have the same calculus capability with lower frecuency. The first one is specialized in digital signal processing and the other one is a general purpose processor. In order to materialize this proposal we will use a board called BeagleBoard which is based on a multicore processor called OMAP3530 from Texas Instrument. This processor includes two cores: ARM Cortex-A8 and a TMS320C64+ DSP core. Changing clock frequency and supply voltage is allowed by OMAP3530, we can decrease the power consumption on this way. On the other hand, MPlayer will be used as video player. It includes a scalable video decoder which let us changing dynamically the resolution or frames per second rate of the video in order to show it later. This player will be executed by ARM core but this is not optimized for this task, for that reason, DSP core will be used to decoding video. The target of this final career project is being able to choose which part of the video is decoded each moment while decoder is executed by DSP and Mplayer by ARM. It will be able to change in real time the video quality, resolution and frames per second that user want to show. On this way, reducing the computational charge within the processor will be possible.

El sistema de grabaci��n y reproducci��n sonora ambiof��nico

Este proyecto fin de carrera trata del sistema de grabaci��n y reproducci��n sonora ambiof��nico, destacar que este sistema y la tecnolog��a que emplea es de dominio p��blico. La ambiofon��a se basa en un amalgama de investigaciones recientes y de los ya bien sabidos principios psicoac��sticos y binaurales. Estos avances han expandido nuevas fronteras en lo concerniente a la grabaci��n y reproducci��n de audio, as�� como de presentar al oyente un campo sonoro a la entrada de sus o��dos lo m��s parecido posible al campo sonoro al que se expondr��a al oyente en el momento y lugar de la toma de sonido, es decir, reconstruye un campo sonora binaural. Este sistema ha podido desarrollarse, de una manera bastante satisfactoria, gracias a todos los estudios y textos anteriores en materia de psicoac��stica y del mecanismo de escucha humano. Otro factor gracias al cual es posible y asequible, tanto el desarrollo como el disfrute de esta tecnolog��a, es el hecho que en nuestros d��as es muy econ��mico disponer de ordenadores lo suficientemente potentes y r��pidos para realizar el procesado de se��ales que se requiere de una manera bastante r��pida. Los desarrolladores de dicha tecnolog��a han publicado diversos documentos y archivos descargables de la red con aplicaciones para la implementaci��n de sistemas ambiof��nicos de manera gratuita para uso privado. El sistema ambiof��nico se basa en la combinaci��n de factores psicoac��sticos ignorados o subestimados y lo ya sabido sobre las propiedades ac��sticas de salas, tanto de salas en las que tienen lugar las ejecuciones musicales (auditorios, teatros, salas de conciertos...), como de salas de escucha (salones de domicilios, controles de estudios...). En la parte pr��ctica del proyecto se van a realizar una serie de grabaciones musicales empleando tanto t��cnicas estereof��nicas tradicionales como ambiof��nicas de grabaci��n con el fin de describir y comparar ambas t��cnicas microf��nicas. Tambi��n servir�� para estudiar hasta que punto es favorable subjetivamente para el oyente el hecho de realizar la toma de sonido teniendo en cuenta las propiedades del sistema de reproducci��n ambiof��nico. Esta comparaci��n nos dar�� una idea de hasta donde se puede llegar, en cuanto a sensaci��n de realidad para el oyente, al tener en cuenta durante el proceso de grabaci��n efectos como la respuesta del pabell��n auditivo del oyente, la cual es ��nica, y que posteriormente la diafon��a interaural va a ser cancelada mediante un procesado digital de se��al. ABSTRACT. This final project is about the ambiophonic recording and playback system, note that this system and the technology it uses is of public domain. Ambiophonics is based on an amalgam of recent research and to the well known and binaural psychoacoustic principles. These advances have expanded new frontiers with regard to the audio recording and playback, as well as to present the listener a sound field at the entrance of their ears as close as possible to the sound field that would the listener be exposed to at the time and place of the mucial interpretation, so we can say that ambiophonics reconstructs a binaural sound field . This system has been developed, in a fairly satisfactory way, thanks to all the studies and previous texts on psychoacoustics and human listening mechanism. Another factor by which it is possible and affordable, both the development and the enjoyment of this technology, is the fact that in our days is inexpensive to usres to own computers that are powerful and fast enough to perform the signal processing that is required in a short time. The developers of this technology have published several documents and downloadable files on the network with applications for ambiophonics system implementation for free. Ambiophonics is based on a combination of factors ignored or underestimated psychoacousticly and what is already known about the acoustic properties of rooms, including rooms where musical performances take place (auditoriums, theaters, concert halls...), and listening rooms (concet halls, studios controls...). In the practical part of the project will be making a series of musical recordings using both traditional stereo recording techniques and recording techiniques compatible with ambiophonics in order to describe and compare both recording techniques. It will also examine to what extent is subjectively favorable for the listener the fact of considering the playback system properties of ambiophonics during the recording stage. This comparison will give us an idea of how far can we get, in terms of sense of reality to the listener, keeping in mind during the recording process the effects introduced by the response of the ear of the listener, which is unique, and that the subsequently interaural crosstalk will be canceled by a digital signal processing.

Design and Validation of an Optimized MB-OFDM Ultra Wideband Transceiver System

Esta tesis est�� incluida dentro del campo del campo de Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband (MB-OFDM UWB), el cual ha adquirido una gran importancia en las comunicaciones inal��mbricas de alta tasa de datos en la ��ltima d��cada. UWB surgi�� con el objetivo de satisfacer la creciente demanda de conexiones inal��mbricas en interiores y de uso dom��stico, con bajo coste y alta velocidad. La disponibilidad de un ancho de banda grande, el potencial para alta velocidad de transmisi��n, baja complejidad y bajo consumo de energ��a, unido al bajo coste de implementaci��n, representa una oportunidad ��nica para que UWB se convierta en una soluci��n ampliamente utilizada en aplicaciones de Wireless Personal Area Network (WPAN). UWB est�� definido como cualquier transmisi��n que ocupa un ancho de banda de m��s de 20% de su frecuencia central, o m��s de 500 MHz. En 2002, la Comisi��n Federal de Comunicaciones (FCC) defini�� que el rango de frecuencias de transmisi��n de UWB legal es de 3.1 a 10.6 GHz, con una energ��a de transmisi��n de -41.3 dBm/Hz. Bajo las directrices de FCC, el uso de la tecnolog��a UWB puede aportar una enorme capacidad en las comunicaciones de corto alcance. Considerando las ecuaciones de capacidad de Shannon, incrementar la capacidad del canal requiere un incremento lineal en el ancho de banda, mientras que un aumento similar de la capacidad de canal requiere un aumento exponencial en la energ��a de transmisi��n. En los ��ltimos a��os, s diferentes desarrollos del UWB han sido extensamente estudiados en diferentes ��reas, entre los cuales, el protocolo de comunicaciones inal��mbricas MB-OFDM UWB est�� considerado como la mejor elecci��n y ha sido adoptado como est��ndar ISO/IEC para los WPANs. Combinando la modulaci��n OFDM y la transmisi��n de datos utilizando las t��cnicas de salto de frecuencia, el sistema MB-OFDM UWB es capaz de soportar tasas de datos con que pueden variar de los 55 a los 480 Mbps, alcanzando una distancia m��xima de hasta 10 metros. Se esperara que la tecnolog��a MB-OFDM tenga un consumo energ��tico muy bajo copando un are muy reducida en silicio, proporcionando soluciones de bajo coste que satisfagan las demandas del mercado. Para cumplir con todas estas expectativas, el desarrollo y la investigaci��n del MBOFDM UWB deben enfrentarse a varios retos, como son la sincronizaci��n de alta sensibilidad, las restricciones de baja complejidad, las estrictas limitaciones energ��ticas, la escalabilidad y la flexibilidad. Tales retos requieren un procesamiento digital de la se��al de ��ltima generaci��n, capaz de desarrollar sistemas que puedan aprovechar por completo las ventajas del espectro UWB y proporcionar futuras aplicaciones inal��mbricas en interiores. Esta tesis se centra en la completa optimizaci��n de un sistema de transceptor de banda base MB-OFDM UWB digital, cuyo objetivo es investigar y dise��ar un subsistema de comunicaci��n inal��mbrica para la aplicaci��n de las Redes de Sensores Inal��mbricas Visuales. La complejidad inherente de los procesadores FFT/IFFT y el sistema de sincronizaci��n as�� como la alta frecuencia de operaci��n para todos los elementos de procesamiento, se convierten en el cuello de la botella para el dise��o y la implementaci��n del sistema de UWB digital en base de banda basado en MB-OFDM de baja energ��a. El objetivo del transceptor propuesto es conseguir baja energ��a y baja complejidad bajo la premisa de un alto rendimiento. Las optimizaciones est��n realizadas tanto a nivel algor��tmico como a nivel arquitectural para todos los elementos del sistema. Una arquitectura hardware eficiente en consumo se propone en primer lugar para aquellos m��dulos correspondientes a n��cleos de computaci��n. Para el procesado de la Transformada R��pida de Fourier (FFT/IFFT), se propone un algoritmo mixed-radix, basado en una arquitectura con pipeline y se ha desarrollado un m��dulo de Decodificador de Viterbi (VD) equilibrado en coste-velocidad con el objetivo de reducir el consumo energ��tico e incrementar la velocidad de procesamiento. Tambi��n se ha implementado un correlador signo-bit simple basado en la sincronizaci��n del tiempo de s��mbolo es presentado. Este correlador es usado para detectar y sincronizar los paquetes de OFDM de forma robusta y precisa. Para el desarrollo de los subsitemas de procesamiento y realizar la integraci��n del sistema completo se han empleado tecnolog��as de ��ltima generaci��n. El dispositivo utilizado para el sistema propuesto es una FPGA Virtex 5 XC5VLX110T del fabricante Xilinx. La validaci��n el propuesta para el sistema transceptor se ha implementado en dicha placa de FPGA. En este trabajo se presenta un algoritmo, y una arquitectura, dise��ado con filosof��a de co-dise��o hardware/software para el desarrollo de sistemas de FPGA complejos. El objetivo principal de la estrategia propuesta es de encontrar una metodolog��a eficiente para el dise��o de un sistema de FPGA configurable optimizado con el empleo del m��nimo esfuerzo posible en el sistema de procedimiento de verificaci��n, por tanto acelerar el periodo de desarrollo del sistema. La metodolog��a de co-dise��o presentada tiene la ventaja de ser f��cil de usar, contiene todos los pasos desde la propuesta del algoritmo hasta la verificaci��n del hardware, y puede ser ampliamente extendida para casi todos los tipos de desarrollos de FPGAs. En este trabajo se ha desarrollado s��lo el sistema de transceptor digital de banda base por lo que la comprobaci��n de se��ales transmitidas a trav��s del canal inal��mbrico en los entornos reales de comunicaci��n sigue requiriendo componentes RF y un front-end anal��gico. No obstante, utilizando la metodolog��a de co-simulaci��n hardware/software citada anteriormente, es posible comunicar el sistema de transmisor y el receptor digital utilizando los modelos de canales propuestos por IEEE 802.15.3a, implementados en MATLAB. Por tanto, simplemente ajustando las caracter��sticas de cada modelo de canal, por ejemplo, un incremento del retraso y de la frecuencia central, podemos estimar el comportamiento del sistema propuesto en diferentes escenarios y entornos. Las mayores contribuciones de esta tesis son: ��� Se ha propuesto un nuevo algoritmo 128-puntos base mixto FFT usando la arquitectura pipeline multi-ruta. Los complejos multiplicadores para cada etapa de procesamiento son dise��ados usando la arquitectura modificada shiftadd. Los sistemas word length y twiddle word length son comparados y seleccionados bas��ndose en la se��al para cuantizaci��n del SQNR y el an��lisis de energ��as. ��� El desempe��o del procesador IFFT es analizado bajo diferentes situaciones aritm��ticas de bloques de punto flotante (BFP) para el control de desbordamiento, por tanto, para encontrar la arquitectura perfecta del algoritmo IFFT basado en el procesador FFT propuesto. ��� Para el sistema de receptor MB-OFDM UWB se ha empleado una sincronizaci��n del tiempo innovadora, de baja complejidad y esquema de compensaci��n, que consiste en funciones de Detector de Paquetes (PD) y Estimaci��n del Offset del tiempo. Simplificando el cross-correlation y maximizar las funciones probables solo a sign-bit, la complejidad computacional se ve reducida significativamente. ��� Se ha propuesto un sistema de decodificadores Viterbi de 64 estados de decisi��n-d��bil usando velocidad base-4 de arquitectura suma-comparaselecciona. El algoritmo Two-pointer Even tambi��n es introducido en la unidad de rastreador de origen con el objetivo de conseguir la eficiencia en el hardware. ��� Se han integrado varias tecnolog��as de ��ltima generaci��n en el completo sistema transceptor basebanda , con el objetivo de implementar un sistema de comunicaci��n UWB altamente optimizado. ��� Un dise��o de flujo mejorado es propuesto para el complejo sistema de implementaci��n, el cual puede ser usado para dise��os de Cadena de puertas de campo programable general (FPGA). El dise��o mencionado no s��lo reduce dram��ticamente el tiempo para la verificaci��n funcional, sino tambi��n provee un an��lisis autom��tico como los errores del retraso del output para el sistema de hardware implementado. ��� Un ambiente de comunicaci��n virtual es establecido para la validaci��n del propuesto sistema de transceptores MB-OFDM. Este m��todo es provisto para facilitar el uso y la conveniencia de analizar el sistema digital de basebanda sin parte frontera anal��gica bajo diferentes ambientes de comunicaci��n. Esta tesis doctoral est�� organizada en seis cap��tulos. En el primer cap��tulo se encuentra una breve introducci��n al campo del UWB, tanto relacionado con el proyecto como la motivaci��n del desarrollo del sistema de MB-OFDM. En el cap��tulo 2, se presenta la informaci��n general y los requisitos del protocolo de comunicaci��n inal��mbrica MBOFDM UWB. En el cap��tulo 3 se habla de la arquitectura del sistema de transceptor digital MB-OFDM de banda base . El dise��o del algoritmo propuesto y la arquitectura para cada elemento del procesamiento est�� detallado en este cap��tulo. Los retos de dise��o del sistema que involucra un compromiso de discusi��n entre la complejidad de dise��o, el consumo de energ��a, el coste de hardware, el desempe��o del sistema, y otros aspectos. En el cap��tulo 4, se ha descrito la co-dise��ada metodolog��a de hardware/software. Cada parte del flujo del dise��o ser�� detallado con algunos ejemplos que se ha hecho durante el desarrollo del sistema. Aprovechando esta estrategia de dise��o, el procedimiento de comunicaci��n virtual es llevado a cabo para probar y analizar la arquitectura del transceptor propuesto. Los resultados experimentales de la co-simulaci��n y el informe sint��tico de la implementaci��n del sistema FPGA son reflejados en el cap��tulo 5. Finalmente, en el cap��tulo 6 se incluye las conclusiones y los futuros proyectos, y tambi��n los resultados derivados de este proyecto de doctorado. ABSTRACT In recent years, the Wireless Visual Sensor Network (WVSN) has drawn great interest in wireless communication research area. They enable a wealth of new applications such as building security control, image sensing, and target localization. However, nowadays wireless communication protocols (ZigBee, Wi-Fi, and Bluetooth for example) cannot fully satisfy the demands of high data rate, low power consumption, short range, and high robustness requirements. New communication protocol is highly desired for such kind of applications. The Ultra Wideband (UWB) wireless communication protocol, which has increased in importance for high data rate wireless communication field, are emerging as an important topic for WVSN research. UWB has emerged as a technology that offers great promise to satisfy the growing demand for low-cost, high-speed digital wireless indoor and home networks. The large bandwidth available, the potential for high data rate transmission, and the potential for low complexity and low power consumption, along with low implementation cost, all present a unique opportunity for UWB to become a widely adopted radio solution for future Wireless Personal Area Network (WPAN) applications. UWB is defined as any transmission that occupies a bandwidth of more than 20% of its center frequency, or more than 500 MHz. In 2002, the Federal Communications Commission (FCC) has mandated that UWB radio transmission can legally operate in the range from 3.1 to 10.6 GHz at a transmitter power of ���41.3 dBm/Hz. Under the FCC guidelines, the use of UWB technology can provide enormous capacity over short communication ranges. Considering Shannon���s capacity equations, increasing the channel capacity requires linear increasing in bandwidth, whereas similar channel capacity increases would require exponential increases in transmission power. In recent years, several different UWB developments has been widely studied in different area, among which, the MB-OFDM UWB wireless communication protocol is considered to be the leading choice and has recently been adopted in the ISO/IEC standard for WPANs. By combing the OFDM modulation and data transmission using frequency hopping techniques, the MB-OFDM UWB system is able to support various data rates, ranging from 55 to 480 Mbps, over distances up to 10 meters. The MB-OFDM technology is expected to consume very little power and silicon area, as well as provide low-cost solutions that can satisfy consumer market demands. To fulfill these expectations, MB-OFDM UWB research and development have to cope with several challenges, which consist of high-sensitivity synchronization, low- complexity constraints, strict power limitations, scalability, and flexibility. Such challenges require state-of-the-art digital signal processing expertise to develop systems that could fully take advantages of the UWB spectrum and support future indoor wireless applications. This thesis focuses on fully optimization for the MB-OFDM UWB digital baseband transceiver system, aiming at researching and designing a wireless communication subsystem for the Wireless Visual Sensor Networks (WVSNs) application. The inherent high complexity of the FFT/IFFT processor and synchronization system, and high operation frequency for all processing elements, becomes the bottleneck for low power MB-OFDM based UWB digital baseband system hardware design and implementation. The proposed transceiver system targets low power and low complexity under the premise of high performance. Optimizations are made at both algorithm and architecture level for each element of the transceiver system. The low-power hardwareefficient structures are firstly proposed for those core computation modules, i.e., the mixed-radix algorithm based pipelined architecture is proposed for the Fast Fourier Transform (FFT/IFFT) processor, and the cost-speed balanced Viterbi Decoder (VD) module is developed, in the aim of lowering the power consumption and increasing the processing speed. In addition, a low complexity sign-bit correlation based symbol timing synchronization scheme is presented so as to detect and synchronize the OFDM packets robustly and accurately. Moreover, several state-of-the-art technologies are used for developing other processing subsystems and an entire MB-OFDM digital baseband transceiver system is integrated. The target device for the proposed transceiver system is Xilinx Virtex 5 XC5VLX110T FPGA board. In order to validate the proposed transceiver system in the FPGA board, a unified algorithm-architecture-circuit hardware/software co-design environment for complex FPGA system development is presented in this work. The main objective of the proposed strategy is to find an efficient methodology for designing a configurable optimized FPGA system by using as few efforts as possible in system verification procedure, so as to speed up the system development period. The presented co-design methodology has the advantages of easy to use, covering all steps from algorithm proposal to hardware verification, and widely spread for almost all kinds of FPGA developments. Because only the digital baseband transceiver system is developed in this thesis, the validation of transmitting signals through wireless channel in real communication environments still requires the analog front-end and RF components. However, by using the aforementioned hardware/software co-simulation methodology, the transmitter and receiver digital baseband systems get the opportunity to communicate with each other through the channel models, which are proposed from the IEEE 802.15.3a research group, established in MATLAB. Thus, by simply adjust the characteristics of each channel model, e.g. mean excess delay and center frequency, we can estimate the transmission performance of the proposed transceiver system through different communication situations. The main contributions of this thesis are: ��� A novel mixed radix 128-point FFT algorithm by using multipath pipelined architecture is proposed. The complex multipliers for each processing stage are designed by using modified shift-add architectures. The system wordlength and twiddle word-length are compared and selected based on Signal to Quantization Noise Ratio (SQNR) and power analysis. ��� IFFT processor performance is analyzed under different Block Floating Point (BFP) arithmetic situations for overflow control, so as to find out the perfect architecture of IFFT algorithm based on the proposed FFT processor. ��� An innovative low complex timing synchronization and compensation scheme, which consists of Packet Detector (PD) and Timing Offset Estimation (TOE) functions, for MB-OFDM UWB receiver system is employed. By simplifying the cross-correlation and maximum likelihood functions to signbit only, the computational complexity is significantly reduced. ��� A 64 state soft-decision Viterbi Decoder system by using high speed radix-4 Add-Compare-Select architecture is proposed. Two-pointer Even algorithm is also introduced into the Trace Back unit in the aim of hardware-efficiency. ��� Several state-of-the-art technologies are integrated into the complete baseband transceiver system, in the aim of implementing a highly-optimized UWB communication system. ��� An improved design flow is proposed for complex system implementation which can be used for general Field-Programmable Gate Array (FPGA) designs. The design method not only dramatically reduces the time for functional verification, but also provides automatic analysis such as errors and output delays for the implemented hardware systems. ��� A virtual communication environment is established for validating the proposed MB-OFDM transceiver system. This methodology is proved to be easy for usage and convenient for analyzing the digital baseband system without analog frontend under different communication environments. This PhD thesis is organized in six chapters. In the chapter 1 a brief introduction to the UWB field, as well as the related work, is done, along with the motivation of MBOFDM system development. In the chapter 2, the general information and requirement of MB-OFDM UWB wireless communication protocol is presented. In the chapter 3, the architecture of the MB-OFDM digital baseband transceiver system is presented. The design of the proposed algorithm and architecture for each processing element is detailed in this chapter. Design challenges of such system involve trade-off discussions among design complexity, power consumption, hardware cost, system performance, and some other aspects. All these factors are analyzed and discussed. In the chapter 4, the hardware/software co-design methodology is proposed. Each step of this design flow will be detailed by taking some examples that we met during system development. Then, taking advantages of this design strategy, the Virtual Communication procedure is carried out so as to test and analyze the proposed transceiver architecture. Experimental results from the co-simulation and synthesis report of the implemented FPGA system are given in the chapter 5. The chapter 6 includes conclusions and future work, as well as the results derived from this PhD work.

Vista general del modelado del sistema auditivo

El objetivo principal del presente proyecto es proporcionar al ingeniero de telecomunicaciones una visi��n general de las t��cnicas que se utilizan en el modelado del sistema auditivo. El modelado del sistema auditivo se realiza con los siguientes objetivos: a) Interpretar medidas directas, b)unificar el entendimiento de diferentes fen��menos, c) guiar estrategias de amplificaci��n para suplir p��rdidas auditivas y d) tener predicciones experimentalmente comprobables de comportamientos, con diferentes niveles de complejidad. En este trabajo se tratar��n y explicar��n brevemente las diferentes t��cnicas utilizadas para modelar las partes del sistema auditivo, desde las analog��as electroac��sticas, modelos biof��sicos, binaurales, hasta la implementaci��n de filtros auditivos mediante procesado de se��al. Podemos concluir que el modelado mediante analog��as electroac��sticas permite una r��pida implementaci��n y entendimiento, pero tiene ciertas limitaciones. Las simulaciones mediante an��lisis num��ricos son precisas y de gran utilidad tanto para del o��do medio como para el interno. El procesado de se��al es el procedimiento m��s completo y utilizado ya que permite modelar o��do externo y medio adem��s de permitir la implementaci��n de filtros cocleares muy precisos y coherentes con la realidad incluy��ndolos en modelos perceptivos. ABSTRACT. The main aim of the Project is to provide the Telecommunications Engineer an overview about the approaches for modelling the auditory system. The auditory system modelling is done for the next objectives: a) Interpret direct measures, b) Understand different phenomena c) get strategies of amplification for hearing impaired people and d) Obtain testable predictions experimentally about some behaviors with different complexity levels. Inside this document, several approaches about modeling of the auditory system parts will be explained: analog circuits, biophysics models, binaural models, and auditory filters made through signal processing. In conclusion, analog circuits are made quickly and they are easier to understand but they have many limitations. Simulations through numerical analysis are accurate and useful in middle and inner ear models. Signal processing is the more versatile approach because it lets to make a model of external and middle ear and then it allows to make complex auditory filters. Perceptive models can be made entirely through this method.

A general stability criterion for switched linear systems having stable and unstable subsystems

We report conditions on a switching signal that guarantee that solutions of a switched linear systems converge asymptotically to zero. These conditions are apply to continuous, discrete-time and hybrid switched linear systems, both those having stable subsystems and mixtures of stable and unstable subsystems.

A stochastic model updating method for parameter variability quantification based on response surface models and Monte Carlo simulation

Stochastic model updating must be considered for quantifying uncertainties inherently existing in real-world engineering structures. By this means the statistical properties,instead of deterministic values, of structural parameters can be sought indicating the parameter variability. However, the implementation of stochastic model updating is much more complicated than that of deterministic methods particularly in the aspects of theoretical complexity and low computational efficiency. This study attempts to propose a simple and cost-efficient method by decomposing a stochastic updating process into a series of deterministic ones with the aid of response surface models and Monte Carlo simulation. The response surface models are used as surrogates for original FE models in the interest of programming simplification, fast response computation and easy inverse optimization. Monte Carlo simulation is adopted for generating samples from the assumed or measured probability distributions of responses. Each sample corresponds to an individual deterministic inverse process predicting the deterministic values of parameters. Then the parameter means and variances can be statistically estimated based on all the parameter predictions by running all the samples. Meanwhile, the analysis of variance approach is employed for the evaluation of parameter variability significance. The proposed method has been demonstrated firstly on a numerical beam and then a set of nominally identical steel plates tested in the laboratory. It is found that compared with the existing stochastic model updating methods, the proposed method presents similar accuracy while its primary merits consist in its simple implementation and cost efficiency in response computation and inverse optimization.

Efficient random variable generation: ratio of uniforms and polar rejection sampling

Monte Carlo techniques, which require the generation of samples from some target density, are often the only alternative for performing Bayesian inference. Two classic sampling techniques to draw independent samples are the ratio of uniforms (RoU) and rejection sampling (RS). An efficient sampling algorithm is proposed combining the RoU and polar RS (i.e. RS inside a sector of a circle using polar coordinates). Its efficiency is shown in drawing samples from truncated Cauchy and Gaussian random variables, which have many important applications in signal processing and communications. RESUMEN. M��todo eficiente para generar algunas variables aleatorias de uso com��n en procesado de se��al y comunicaciones (por ejemplo, Gaussianas o Cauchy truncadas) mediante la combinaci��n de dos t��cnicas: "ratio of uniforms" y "rejection sampling".

Implementaci��n y configuraci��n de un receptor de radio definido por software (SDR) para estudios de propagaci��n

The constant development of digital systems in radio communications demands the adaptation of the current receiving equipment to the new technologies. In this context, a new Software Defined Radio based receiver is being implemented with the aim of carrying out different experiments to analyze the propagation of signals through the atmosphere from a satellite beacon. The receiver selected for this task is the PERSEUS SDR from the Italian company Microtelecom s.r.l. It is a software defined VLF-LF-MF-HF receiver based on an outstanding direct sampling digital architecture which features a 14 bit 80 MSamples/s analog-to-digital converter, a high-performance FPGA-based digital down-converter and a high-speed 480 Mbit/s USB2.0 PC interface. The main goal is to implement the related software and adapt the new receiver to the current working environment. In this paper, SDR technology guidelines are given and PERSEUS receiver digital signal processing is presented with the most remarkable results.