QCA Systolic array design

Quantum-dot Cellular Automata (QCA) technology is a promising potential alternative to CMOS technology. To explore the characteristics of QCA and suitable design methodologies, digital circuit design approaches have been investigated. Due to the inherent wire delay in QCA, pipelined architectures appear to be a particularly suitable design technique. Also, because of the pipeline nature of QCA technology, it is not suitable for complicated control system design. Systolic arrays take advantage of pipelining, parallelism and simple local control. Therefore, an investigation into these architectures in QCA technology is provided in this paper. Two case studies, (a matrix multiplier and a Galois Field multiplier) are designed and analyzed based on both multilayer and coplanar crossings. The performance of these two types of interconnections are compared and it is found that even though coplanar crossings are currently more practical, they tend to occupy a larger design area and incur slightly more delay. A general semi-conductor QCA systolic array design methodology is also proposed. It is found that by applying a systolic array structure in QCA design, significant benefits can be achieved particularly with large systolic arrays, even more so than when applied in CMOS-based technology.

Brief Report: Faces cause less distraction in Autism

Individuals with autism have difficulties interpreting face cues that contribute to deficits of social communication.When faces need to be processed for meaning they fail to capture and hold the attention of individuals with autism. In the current study we illustrate that faces fail to capture attention in a typical manner even when they are non-functional to task completion. In a visual search task with a present butterfly target an irrelevant face distractersignificantly slows performance of typical individuals.However, participants with autism (n = 28; mean 10 years 4 months) of comparable non-verbal ability are not distracted by the faces. Interestingly, there is a significant relationship between level of functioning on the autism spectrum and degree of face capture or distraction.

The Architecture of Home in Cairo: Socio-Spatial Practice of the Hawari's Everyday Life

The hawari of Cairo - narrow non-straight alleyways - are the basic urban units that have formed the medieval city since its foundation back in 969 AD. Until early in the C20th, they made up the primary urban divisions of the city and were residential in nature. Contemporary hawari, by contrast, are increasingly dominated by commercial and industrial activity. This medieval urban maze of extremely short, broken, zigzag streets and dead ends are defensible territories, powerful institutions, and important social systems. While the hawari have been studied as an exemplar for urban structure of medieval Islamic urbanism, and as individual building typologies, this book is the first to examine in detail the socio-spatial practice of the architecture of home in the city. It investigates how people live, communicate and relate to each other within their houses or shared spaces of the alleys, and in doing so, to uncover several new socio-spatial dimensions and meanings in this architectural form.

In an attempt to re-establish the link between architecture past and present, and to understand the changing social needs of communities, this book uncovers the notion of home as central to understand architecture in such a city with long history as Cairo. It firstly describes the historical development of the domestic spaces (indoor and outdoor), and provides an inclusive analysis of spaces of everyday activities in the hawari of old Cairo. It then broadens its analysis to other parts of the city, highlighting different customs and representations of home in the city at large. Cairo, in the context of this book, is represented as the most sophisticated urban centre in the Middle East with different and sometimes contrasting approaches to the architecture of home, as a practice and spatial system.

In order to analyse the complexity and interconnectedness of the components and elements of the hawari as a 'collective home', it layers its narratives of architectural and social developments as a domestic environment over the past two hundred years, and in doing so, explores the in-depth social meaning and performance of spaces, both private and public.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

Efficient advanced encryption standard implementation using lookup and normal basis

A new type of advanced encryption standard (AES) implementation using a normal basis is presented. The method is based on a lookup technique that makes use of inversion and shift registers, which leads to a smaller size of lookup for the S-box than its corresponding implementations. The reduction in the lookup size is based on grouping sets of inverses into conjugate sets which in turn leads to a reduction in the number of lookup values. The above technique is implemented in a regular AES architecture using register files, which requires less interconnect and area and is suitable for security applications. The results of the implementation are competitive in throughput and area compared with the corresponding solutions in a polynomial basis.