Simple trapped-ion architecture for high-fidelity Toffoli gates

We discuss a simple architecture for a quantum TOFFOLI gate implemented using three trapped ions. The gate, which, in principle, can be implemented with a single laser-induced operation, is effective under rather general conditions and is strikingly robust (within any experimentally realistic range of values) against dephasing, heating, and random fluctuations of the Hamiltonian parameters. We provide a full characterization of the unitary and noise-affected gate using three-qubit quantum process tomography.

An On Demand Queue Management Architecture for a Programmable Traffic Manager

A queue manager (QM) is a core traffic management (TM) function used to provide per-flow queuing in access andmetro networks; however current designs have limited scalability. An on-demand QM (OD-QM) which is part of a new modular field-programmable gate-array (FPGA)-based TM is presented that dynamically maps active flows to the available physical resources; its scalability is derived from exploiting the observation that there are only a few hundred active flows in a high speed network. Simulations with real traffic show that it is a scalable, cost-effective approach that enhances per-flow queuing performance, thereby allowing per-flow QM without the need for extra external memory at speeds up to 10 Gbps. It utilizes 2.3%–16.3% of a Xilinx XC5VSX50t FPGA and works at 111 MHz.

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection

The most promising way to maintain reliable data transfer across the rapidly fluctuating channels used by next generation multiple-input multiple-output communications schemes is to exploit run-time variable modulation and antenna configurations. This demands that the baseband signal processing architectures employed in the communications terminals must provide low cost and high performance with runtime reconfigurability. We present a softcore-processor based solution to this issue, and show for the first time, that such programmable architectures can enable real-time data operation for cutting-edge standards
such as 802.11n; furthermore, by exploiting deep processing pipelines and interleaved task execution, the cost and performance of these architectures is shown to be on a par with traditional dedicated circuit based solutions. We believe this to be the first such programmable architecture to achieve this, and the combination of implementation efficiency and programmability makes this implementation style the most promising approach for hosting such dynamic architectures.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

Web crippling behaviour of cold-formed steel channel sections with offset web holes subjected to interior-two-flange loading

Cold-formed steel sections are often used as wall studs or floor joists; such sections often include web holes for ease of installation of the services. Cold-formed steel design codes, however, do not consider the effect of such web holes. In this paper, a combination of experimental tests and non-linear elasto-plastic finite element analyses are used to investigate the effect of such holes on web crippling under interior-two-flange (ITF) loading conditions; the cases of both flange fastened and flange unfastened are considered. A good agreement between the experimental tests and finite element analyses was obtained. The finite element model was then used for the purposes of a parametric study on the effect of different sizes and position of holes in the web. It was demonstrated that the main factors influencing the web crippling strength are the ratio of the hole depth to the depth of the web, and the ratio of the distance from the edge of the bearing to the flat depth of web. Design recommendations in the form of web crippling strength reduction factors are proposed, that are conservative to both the experimental and finite element results.