937 resultados para lab-on-a-chip systems
Resumo:
A linear, tunable CMOS transconductance stage is introduced. Drain voltage of the input transistor operating in triode region is settled by a regulation loop and a first-order linear relationship between g(m) and a de bias voltage is achieved. In addition to easy tuning, this technique offers circuit simplicity, wide dynamic range, high input and output impedances and low consumption. The transconductor is presented on both single-ended and fully-differential versions. A 3rd-order elliptical low-pass g(m)-C filter with a nominal roll-off frequency of 2MHz is used as one example for the many applications of the proposed transconductor. SPICE data describe circuits performances and filter tunabilily Passband is tuned at a rate of 2.36KHz/mV and good linearity is indicated by a 0.89% THD for an 800mV(p-p) balanced-driven input.
Resumo:
The crossflow filtration process differs of the conventional filtration by presenting the circulation flow tangentially to the filtration surface. The conventional mathematical models used to represent the process have some limitations in relation to the identification and generalization of the system behavior. In this paper, a system based on fuzzy logic systems is developed to overcome the problems usually found in the conventional mathematical models. Imprecisions and uncertainties associated with the measurements made on the system are automatically incorporated in the fuzzy approach. Simulation results are presented to justify the validity of the proposed approach.
Resumo:
An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.
Resumo:
A constructive heuristic algorithm to solve the transmission system expansion planning problem is proposed with the aim of circumventing some critical problems of classical heuristic algorithms that employ relaxed mathematical models to calculate a sensitivity index that guides the circuit additions. The proposed heuristic algorithm is in a branch-and-bound algorithm structure, which can be used with any planning model, such as Transportation model, DC model, AC model or Hybrid models. Tests of the proposed algorithm are presented on real Brazilian systems.
Resumo:
Estudou-se o comportamento de diferentes espécies de maracujazeiro Passiflora spp disponíveis em nosso meio, quando inoculadas com o nematóide formador de galhas Meloidogyne incognita. As avaliações foram feitas 80 dias após a inoculação do parasito, com base nos números de galhas e de ootecas observados nos sistemas radiculares das plantas. Verificou-se que Passiflora alata, P. giberti, P. maliformis e P. serrato digitata mostraram elevada suscetibilidade, enquanto que P. caerulea, P. edulis e P. edulis f. flavicarpa foram bastante resistentes.
Resumo:
A method for optimal transmission network expansion planning is presented. The transmission network is modelled as a transportation network. The problem is solved using hierarchical Benders decomposition in which the problem is decomposed into master and slave subproblems. The master subproblem models the investment decisions and is solved using a branch-and-bound algorithm. The slave subproblem models the network operation and is solved using a specialised linear program. Several alternative implementations of the branch-and-bound algorithm have been rested. Special characteristics of the transmission expansion problem have been taken into consideration in these implementations. The methods have been tested on various test systems available in the literature.
Resumo:
This paper presents some definitions and concepts of the Instantaneous Complex Power Theory [1] which is a new approach for the Akagi's Instantaneous Reactive Power Theory [2].The powers received by an ideal inductor are interpreted and the knowledge of the actual nature of these powers may lead to changes of the conventional electrical power concepts.
Resumo:
The Backpropagation Algorithm (BA) is the standard method for training multilayer Artificial Neural Networks (ANN), although it converges very slowly and can stop in a local minimum. We present a new method for neural network training using the BA inspired on constructivism, an alphabetization method proposed by Emilia Ferreiro based on Piaget philosophy. Simulation results show that the proposed configuration usually obtains a lower final mean square error, when compared with the standard BA and with the BA with momentum factor.
Resumo:
An algorithm for adaptive IIR filtering that uses prefiltering structure in direct form is presented. This structure has an estimation error that is a linear function of the coefficients. This property greatly simplifies the derivation of gradient-based algorithms. Computer simulations show that the proposed structure improves convergence speed.
Resumo:
The performance of the three-phase core type transformers, under AC/DC double excitation is discussed in this work. It is presented a mathematical model that considers the mutual coupling between phases and the magnetic nonlinearity. The validity of the proposed model is verified by means of the experimental and simulated results.
Resumo:
This paper describes a speech enhancement system (SES) based on a TMS320C31 digital signal processor (DSP) for real-time application. The SES algorithm is based on a modified spectral subtraction method and a new speech activity detector (SAD) is used. The system presents a medium computational load and a sampling rate up to 18 kHz can be used. The goal is load and a sampling rate up to 18 kHz can be used. The goal is to use it to reduce noise in an analog telephone line.
Resumo:
The iterative quadratic maximum likelihood IQML and the method of direction estimation MODE are well known high resolution direction-of-arrival DOA estimation methods. Their solutions lead to an optimization problem with constraints. The usual linear constraint presents a poor performance for certain DOA values. This work proposes a new linear constraint applicable to both DOA methods and compare their performance with two others: unit norm and usual linear constraint. It is shown that the proposed alternative performs better than others constraints. The resulting computational complexity is also investigated.
Resumo:
The objective of this work is the development of a methodology for electric load forecasting based on a neural network. Here, it is used Backpropagation algorithm with an adaptive process based on fuzzy logic. This methodology results in fast training, when compared to the conventional formulation of Backpropagation algorithm. Results are presented using data from a Brazilian Electric Company and the performance is very good for the proposal objective.
Resumo:
This paper presents a high speed current mode CMOS comparator. The comparator was optimized for allows wide range input current 1mA, ±0.5uA resolution and has fast response. This circuit was implemented with 0.8μm CMOS n-well process with area of 120μm × 105μm and operates with 3.3V(±1.65V).
Resumo:
A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.