A Framework for Context-Driven End-to-End QoS Control in Converged Next Generation Networks”

This paper presents a framework for context-driven policy-based QoS control and end-to-end resource management in converged next generation networks. The Converged Networks QoS Framework (CNQF) is being developed within the IU-ATC project, and comprises distributed functional entities whose instances co-ordinate the converged network infrastructure to facilitate scalable and efficient end-to-end QoS management. The CNQF design leverages aspects of TISPAN, IETF and 3GPP policy-based management architectures whilst also introducing important innovative extensions to support context-aware QoS control in converged networks. The framework architecture is presented and its functionalities and operation in specific application scenarios are described.

Using Mesh-Geometry Relationships to Transfer Analysis Models between CAE Tools

Integrating analysis and design models is a complex task due to differences between the models and the architectures of the toolsets used to create them. This complexity is increased with the use of many different tools for specific tasks during an analysis process. In this work various design and analysis models are linked throughout the design lifecycle, allowing them to be moved between packages in a way not currently available. Three technologies named Cellular Modeling, Virtual Topology and Equivalencing are combined to demonstrate how different finite element meshes generated on abstract analysis geometries can be linked to their original geometry. Establishing the equivalence relationships between models enables analysts to utilize multiple packages for specialist tasks without worrying about compatibility issues or rework.

A Note on Networks of Collaboration in Multimarket Oligopolies

In this note, we extend the Goyal and Joshi’s model of collaboration networks in oligopoly to multi-market situations. We examine the incentive of firms to form links and the architectures of the resulting equilibrium networks in this setting. We then present some results on efficient networks.

The ParaPhrase Project:Parallel patterns for adaptive heterogeneous multicore systems

This paper describes the ParaPhrase project, a new 3-year targeted research project funded under EU Framework 7 Objective 3.4 (Computer Systems), starting in October 2011. ParaPhrase aims to follow a new approach to introducing parallelism using advanced refactoring techniques coupled with high-level parallel design patterns. The refactoring approach will use these design patterns to restructure programs defined as networks of software components into other forms that are more suited to parallel execution. The programmer will be aided by high-level cost information that will be integrated into the refactoring tools. The implementation of these patterns will then use a well-understood algorithmic skeleton approach to achieve good parallelism. A key ParaPhrase design goal is that parallel components are intended to match heterogeneous architectures, defined in terms of CPU/GPU combinations, for example. In order to achieve this, the ParaPhrase approach will map components at link time to the available hardware, and will then re-map them during program execution, taking account of multiple applications, changes in hardware resource availability, the desire to reduce communication costs etc. In this way, we aim to develop a new approach to programming that will be able to produce software that can adapt to dynamic changes in the system environment. Moreover, by using a strong component basis for parallelism, we can achieve potentially significant gains in terms of reducing sharing at a high level of abstraction, and so in reducing or even eliminating the costs that are usually associated with cache management, locking, and synchronisation. © 2013 Springer-Verlag Berlin Heidelberg.

Analysis of Dependence Tracking Algorithms for Task Dataflow Execution

Processor architectures has taken a turn towards many-core processors, which integrate multiple processing cores on a single chip to increase overall performance, and there are no signs that this trend will stop in the near future. Many-core processors are harder to program than multi-core and single-core processors due to the need of writing parallel or concurrent programs with high degrees of parallelism. Moreover, many-cores have to operate in a mode of strong scaling because of memory bandwidth constraints. In strong scaling increasingly finer-grain parallelism must be extracted in order to keep all processing cores busy.

Task dataflow programming models have a high potential to simplify parallel program- ming because they alleviate the programmer from identifying precisely all inter-task de- pendences when writing programs. Instead, the task dataflow runtime system detects and enforces inter-task dependences during execution based on the description of memory each task accesses. The runtime constructs a task dataflow graph that captures all tasks and their dependences. Tasks are scheduled to execute in parallel taking into account dependences specified in the task graph.

Several papers report important overheads for task dataflow systems, which severely limits the scalability and usability of such systems. In this paper we study efficient schemes to manage task graphs and analyze their scalability. We assume a programming model that supports input, output and in/out annotations on task arguments, as well as commutative in/out and reductions. We analyze the structure of task graphs and identify versions and generations as key concepts for efficient management of task graphs. Then, we present three schemes to manage task graphs building on graph representations, hypergraphs and lists. We also consider a fourth edge-less scheme that synchronizes tasks using integers. Analysis using micro-benchmarks shows that the graph representation is not always scalable and that the edge-less scheme introduces least overhead in nearly all situations.

Intermittency, quasiperiodicity and chaos in probe-induced ferroelectric domain switching

Memristive materials and devices, which enable information storage and processing on one and the same physical platform, offer an alternative to conventional von Neumann computation architectures. Their continuous spectra of states with intricate field-history dependence give rise to complex dynamics, the spatial aspect of which has not been studied in detail yet. Here, we demonstrate that ferroelectric domain switching induced by a scanning probe microscopy tip exhibits rich pattern dynamics, including intermittency, quasiperiodicity and chaos. These effects are due to the interplay between tip-induced polarization switching and screening charge dynamics, and can be mapped onto the logistic map. Our findings may have implications for ferroelectric storage, nanostructure fabrication and transistor-less logic.

Network Topology, Higher Orders of Stability and Efficiency

Stable networks of order r where r is a natural number refer to those networks that are immune to coalitional deviation of size r or less. In this paper, we introduce stability of a finite order and examine its relation with efficient networks under anonymous and component additive value functions and the component-wise egalitarian allocation rule. In particular, we examine shapes of networks or network architectures that would resolve the conflict between stability and efficiency in the sense that if stable networks assume those shapes they would be efficient and if efficient networks assume those shapes, they would be stable with minimal further restrictions on value functions.

ASIP: developments, challenges and trends

Application Specific Instruction Set Processor (ASIP) becomes an attractive substitute for ASIC as transistor density, logic complexity and market competition boost. Similar to ASIC, ASIP is based on customized and tailored architectures. In this way, ASIP delivers high performances with low overheads on cost and power whilst taking the advantages of high flexibility and fast time-to-market as a processor-based solution. To demonstrate this effective solution for embedded applications, this paper performs an overall investigation on ASIP's developments, challenges, trends in terms of architectures and design methodologies.

Bus Transportation – Córas Iompair Éireann and Michael Scott

The book acts as a companion to the Irish pavilion at the 2014 Venice Biennale for Architecture. This chapter examines the context of roads transport and then analyses how its architectural infrastructure developed in this period, concentrating on the work carried out mainly by one Irish firm: Michael Scott and Partners.

Simple high sensitivity wireless transceiver

This article describes an extremely simple wireless transceiver, comprising of only a low Q VCO and a phase locked loop IC. It is experimentally shown to, simultaneously, transmit an 8-dBm CW interrogation signal, while concurrently demodulating a phase modulated received signal with sensitivity levels of -120 dBm. This makes the performance similar to conventional transceivers, which require complex superheterodyne type architectures and also require a means to provide a high isolation separate the transmit/receive signals (such as a circulator). 

Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems

Abstract—Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memory
access (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implement
the proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to
67.1%, under a power cap.

A Framework for Prototyping and Reasoning about Distributed Systems

A framework supporting fast prototyping as well as tuning of distributed applications is presented. The approach is based on the adoption of a formal model that is used to describe the orchestration of distributed applications. The formal model (Orc by Misra and Cook) can be used to support semi-formal reasoning about the applications at hand. The paper describes how the framework can be used to derive and evaluate alternative orchestrations of a well know parallel/distributed computation pattern; and shows how the same formal model can be used to support generation of prototypes of distributed applications skeletons directly from the application description.

A network architectural style for real-time systems: NaSr

Inter-component communication has always been of great importance in the design of software architectures and connectors have been considered as first-class entities in many approaches [1][2][3]. We present a novel architectural style that is derived from the well-established domain of computer networks. The style adopts the inter-component communication protocol in a novel way that allows large scale software reuse. It mainly targets real-time, distributed, concurrent, and heterogeneous systems.