Runtime Support for Adaptive Power Capping on Heterogeneous SoCs

Power capping is a fundamental method for reducing the energy consumption of a wide range of modern computing environments, ranging from mobile embedded systems to datacentres. Unfortunately, maximising performance and system efficiency under static power caps remains challenging, while maximising performance under dynamic power caps has been largely unexplored. We present an adaptive power capping method that reduces the power consumption and maximizes the performance of heterogeneous SoCs for mobile and server platforms. Our technique combines power capping with coordinated DVFS, data partitioning and core allocations on a heterogeneous SoC with ARM processors and FPGA resources. We design our framework as a run-time system based on OpenMP and OpenCL to utilise the heterogeneous resources. We evaluate it through five data-parallel benchmarks on the Xilinx SoC which allows fully voltage and frequency control. Our experiments show a significant performance boost of 30% under dynamic power caps with concurrent execution on ARM and FPGA, compared to a naive separate approach.

The impact of different power dividers used in a non-uniform planar antenna array

Wireless communications are widely used for various applications, requiring antennas with different features. Often, to achieve the desired radiation pattern, is necessary to employ antenna arrays, using non-uniform excitation on its elements. Power dividers can be used and the best known are the T-junction and the Wilkinson power divider, whose main advantage is the isolation between output ports. In this paper the impact of this isolation on the overall performance of a circularly polarized planar antenna array using non-uniform excitation is investigated. Results show a huge decrease of the array bandwidths either in terms of return loss or in polarization, without resistors. © 2014 IEEE.

Optimizing the renewable generation mix in the portuguese power system based on temporal and spatial diversity

Renewable energy sources (RES) have unique characteristics that grant them preference in energy and environmental policies. However, considering that the renewable resources are barely controllable and sometimes unpredictable, some challenges are faced when integrating high shares of renewable sources in power systems. In order to mitigate this problem, this paper presents a decision-making methodology regarding renewable investments. The model computes the optimal renewable generation mix from different available technologies (hydro, wind and photovoltaic) that integrates a given share of renewable sources, minimizing residual demand variability, therefore stabilizing the thermal power generation. The model also includes a spatial optimization of wind farms in order to identify the best distribution of wind capacity. This methodology is applied to the Portuguese power system.

Thermal control of electronics: Perspectives and prospects

One of the most prominent industrial applications of heat transfer science and engineering has been electronics thermal control. Driven by the relentless increase in spatial density of microelectronic devices, integrated circuit chip powers have risen by a factor of 100 over the past twenty years, with a somewhat smaller increase in heat flux. The traditional approaches using natural convection and forced-air cooling are becoming less viable as power levels increase. This paper provides a high-level overview of the thermal management problem from the perspective of a practitioner, as well as speculation on the prospects for electronics thermal engineering in years to come.

Design, implementation and characterisation of a contactless power transfer system for rotating applications

This paper describes the design, implementation and characterisation of a contactless power transfer system for rotating applications. The power transfer system is based upon a zero-voltage-switched, full-bridge, DC-DC converter, but utilises a non-standard transformer. This transformer allows power transfer between its primary and secondary windings while also allowing free rotation between these windings. The aim of this research is to develop a solution that could replace mechanical slip-rings in certain applications where a non-contacting system would be advantageous. Based upon the design method presented in this paper, a 2 kW prototype system is constructed. Results obtained from testing the 2 kW prototype are presented and discussed. This discussion considers how the performance of the transformer varies with rotation and also the overall efficiency of the system

Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).

An efficient low power FFT implementation for multiband full-rate ultra-wideband (UWB) receivers

This paper discusses the design, implementation and synthesis of an FFT module that has been specifically optimized for use in the OFDM based Multiband UWB system, although the work is generally applicable to many other OFDM based receiver systems. Previous work has detailed the requirements for the receiver FFT module within the Multiband UWB ODFM based system and this paper draws on those requirements coupled with modern digital architecture principles and low power design criteria to converge on our optimized solution. The FFT design obtained in this paper is also applicable for implementation of the transmitter IFFT module therefore only needing one FFT module for half-duplex operation. The results from this paper enable the baseband designers of the 200Mbit/sec variant of Multiband UWB systems (and indeed other OFDM based receivers) using System-on-Chip (SoC), FPGA and ASIC technology to create cost effective and low power solutions biased toward the competitive consumer electronics market.

Systematic selection of analogue redesign method for forward-type digital power converters

This article proposes a systematic approach to determine the most suitable analogue redesign method to be used for forward-type converters under digital voltage mode control. The focus of the method is to achieve the highest phase margin at the particular switching and crossover frequencies chosen by the designer. It is shown that at high crossover frequencies with respect to switching frequency, controllers designed using backward integration have the largest phase margin; whereas at low crossover frequencies with respect to switching frequency, controllers designed using bilinear integration with pre-warping have the largest phase margins. An algorithm has been developed to determine the frequency of the crossing point where the recommended discretisation method changes. An accurate model of the power stage is used for simulation and experimental results from a Buck converter are collected. The performance of the digital controllers is compared to that of the equivalent analogue controller both in simulation and experiment. Excellent closeness between the simulation and experimental results is presented. This work provides a concrete example to allow academics and engineers to systematically choose a discretisation method.

Detection and Identification of Abnormalities in Customer Consumptions in Power Distribution Systems

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Single-phase high power-factor boost ZCS pre-regulator operating in critical conduction mode

This paper presents a new single-phase interleaved high power factor boost pre-regulator operating in critical conduction mode, where the switches and boost diode performing zero-current commutations during its turn-off, eliminating the disadvantages related to the reverse recovery losses and electromagnetic interference problems of the boost diode, when operating in the continuous conduction mode. The interleaving technique is applied in the power cell, providing a significant input current ripple reduction in comparison to discontinuous mode of operation, due to its input current continuous conduction operation. This paper presents a complete modeling for the converter operating in critical conduction mode, resulting in an improved design procedure for interleaved techniques with high input power factor, a complete design procedure, and main simulation results from a design example with two interleaved cells rated at 1kW, 400V output voltage and 220V rms input voltage.

Novel high-power-factor ZCS-PWM preregulators

This paper introduces novel zero-current-switching (ZCS) pulsewidth-modulated (PWM) preregulators based on a new soft-commutation cell, suitable for insulated gate bipolar transistor applications. The active switches in these proposed rectifiers turn on in zero current and turn off in zero current-zero voltage. In addition, the diodes turn on in zero voltage and their reverse-recovery effects over the active switches are negligible. Moreover, based on the proposed cell, an entire family of de-to-de ZCS-PWM converters can be generated, providing conditions to obtain naturally isolated converters, for example, derived buck-boost, Sepic. and Zeta converters. The novel ac-to-dc ZCS-PWM boost and Zeta preregulators are presented in order to verify the operation of this soft-commutation cell, In order to minimize the harmonic contents of the input current, increasing the ac power factor, the average-current-mode control is used, obtaining preregulators with ac power factor near unity and high efficiency at wide load range. The principle of operation, theoretical analysis, design example, and experimental results from test units for the novel preregulators are presented. The new boost preregulator was designed to nominal values of 1.6 kW output power, 220 V(rms) input voltage, 400 V(dc) output voltage, and operating at 20 kHz. The measured efficiency and power factor of the new ZCS-PWM boost preregulator were 96.7% and 0,99, respectively, with an input current total harmonic distortion (THD) equal to 3.42% for an input voltage with THD equal to 1.61%, at rated load, the new ZCS-PWM Zeta preregulator was designed to voltage step-down operation, and the experimental results were obtained from a laboratory prototype rated at 500 W, 220 V(rm), input voltage, 110 V(dc) output voltage, and operating at 50 kHz. The measured efficiency of the new ZCS-PWM Zeta preregulator is approximately 96.9% and the input power factor is 0.98, with an input current THD equal to 19.07% while the input voltage THD is equal to 1.96%, at rated load.

Continuation fast decoupled power flow with secant predictor

The conventional Newton and fast decoupled power flow methods are considered inadequate for obtaining the maximum loading point of power systems due to ill-conditioning problems at and near this critical point. At this point, the Jacobian matrix of the Newton method becomes singular. In addition, it is widely accepted that the P-V and Q-theta decoupling assumptions made for the fast decoupled power flow formulation no longer hold. However, in this paper, it is presented a new fast decoupled power flow that becomes adequate for the computation of the maximum loading point by simply using the reactive power injection of a selected PV bus as a continuation parameter. Besides, fast decoupled methods using V and 0 as parameters and a secant predictor are also presented. These new versions are compared to each other with the purpose of pointing out their features, as well as the influence of reactive power and transformer tap limits. The results obtained for the IEEE systems (14 and 118 buses) show that the characteristics of the conventional method are enhanced and the region of convergence around the singular solution is enlarged.

High power factor dimmable electronic ballast for multiple tubular fluorescent lamps

This paper presents a dimmable electronic ballast designed for multiple fluorescent lamps applications. A ZCS-PWM Boost rectifier and a classical resonant Full-Bridge inverter compose this new electronic ballast, providing conditions for the obtaining of high input power-factor, and soft-switching processes for all semiconductor devices employed in the structure. The instantaneous average input current control technique is employed in the Boost rectifier. Concerning the Full-Bridge inverter, it is controlled by the imposition of phase-shift in the current processed through the sets of resonant filters + lamps, according to an adaptation in a specially designed control IC, called IR2159. Experimental results are presented in order to validate the analyses developed in this paper.

Real power losses reduction and loading margin improvement via continuation method

This letter presents an alternative approach for reducing the total real power losses by using a continuation method. Results for two simple test systems and for the IEEE 57-bus system show that this procedure results in larger voltage stability margin. Besides, the reduction of real power losses obtained with this procedure leads to significant money savings and, simultaneously, to voltage profile improvement. Comparison between the solution of an optimal power flow and the proposed method shows that the latter can provide near optimal results and so, it can be a reasonable alternative to power system voltage stability enhancement.

Variable-Structure Control Design of Switched Systems With an Application to a DC-DC Power Converter

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)