Conversores DC-DC comutados de elevado rendimento para sensores de imagem

Nesta tese de mestrado em engenharia telecomunicações e redes de energia, fez-se um estudo sobre conversores DC-DC comutados de elevado rendimento para sensores de imagem. Onde o principal objetivo é que se desenvolva, em ambiente industrial, um conversor DC-DC de alto rendimento que seja capaz de criar uma tensão inferior à sua alimentação. De salientar que o conversor foi implementado, quase na totalidade, sob a forma de circuito integrado, na tecnologia CMOS 0,35 μm. A implementação deste trabalho foi realizada por meio de um estágio na empresa de sensores de imagem Awaiba. No desenvolvimento do conversor DC-DC inicializou-se o estudo com um regulador de condensadores comutados, com uma arquitetura simples, em que se verificou, através de simulações realizadas num software específico para circuitos integrados - Design Arquitect-IC, que este regulador, apesar de estabilizar a tensão de saída na pretendida, não apresentava alto rendimento, ficando pelos 62%. Na sequência do estudo, na tentativa de melhorar as características do regulador de condensadores comutados, desenvolveu-se um conversor DC-DC com um filtro passa baixo na saída. Verificou-se, através de simulação que este conversor apresentava um rendimento de 92%, onde a sua tensão de alimentação é de 3,3 V e consegue regular na sua saída uma tensão variável entre 1,4 V e 2,2 V, suportando uma corrente máxima de 200 mA. É de referir que o conversor desenvolvido apresenta um tempo de resposta de 20 μs quando ocorre um consumo de corrente com variação em escalão. Sendo um conversor adequado para alimentar sensores de imagem e com elevado rendimento.

Sincronização de múltiplas câmaras e controlo de iluminação sobre uma plataforma FPGA

O objetivo deste projeto foi o de realizar a sincronização de pelo menos quatro câmaras individuais, ajustando dinamicamente o frame rate de operação de cada câmara, tendo por base a família de sensores de imagem CMOS NanEye da empresa Awaiba, numa plataforma FPGA com interface USB3. Durante o projeto analisou-se, com a assistência de um supervisor da Awaiba, o sistema core de captura de imagem existente, baseado em VHDL. Foi estudado e compreendido o princípio do ajuste dinâmico do frame rate das câmaras. Tendo sido então desenvolvido o módulo de controlo da câmara, em VHDL, e um algoritmo de ajuste dinâmico do frame rate, sendo este implementado junto com a plataforma de processamento e interface da FPGA. Foi criado um módulo para efetuar a monitorização da frequência de operação de cada câmara, medindo o período de cada linha numa frame, tendo por base um sinal de relógio de valor conhecido. A frequência é ajustada variando o nível de tensão aplicado ao sensor com base no erro entre o período da linha medido e o período pretendido. Para garantir o funcionamento conjunto de múltiplas câmaras em modo síncrono foi implementada uma interface Master-Slave entre estas. Paralelamente ao módulo anteriormente descrito, implementou-se um sistema de controlo automático de iluminação com base na análise de regiões de interesse em cada frame captada por uma câmara NanEye. A intensidade de corrente aplicada às fontes de iluminação acopladas à câmara é controlada dinamicamente com base no nível de saturação dos pixéis analisados em cada frame. Foram desenvolvidas e implementadas variantes do algoritmo de controlo e o seu desempenho foi avaliado em laboratório. Os resultados obtidos na prática evidenciam que a solução implementada cumpre os requisitos de controlo e ajuste da frequência de operação de múltiplas câmaras. Mostrou ser um método de controlo capaz de manter um erro de sincronização médio de 3,77 μs mesmo na presença de variações de temperatura de aproximadamente 50 °C. Foi também demonstrado que o sistema de controlo de iluminação é capaz de proporcionar uma experiência de visualização adequada, alcançando erros menores que 3% e uma velocidade de ajuste máxima inferior a 1 s.

Conversor CC/CA de alta freqüência baseado em inversores ressonantes com comutação seqüencial para excitação de uma tocha indutiva a plasma térmico

This work describes the study, the analysis, the project methodology and the constructive details of a high frequency DC/AC resonant series converter using sequential commutation techniques for the excitation of an inductive coupled thermal plasma torch. The aim of this thesis is to show the new modulation technique potentialities and to present a technological option for the high-frequency electronic power converters development. The resonant converter operates at 50 kW output power under a 400 kHz frequency and it is constituted by inverter cells using ultra-fast IGBT devices. In order to minimize the turn-off losses, the inverter cells operates in a ZVS mode referred by a modified PLL loop that maintains this condition stable, despite the load variations. The sequential pulse gating command strategy used it allows to operate the IGBT devices on its maximum power limits using the derating and destressing current scheme, as well as it propitiates a frequency multiplication of the inverters set. The output converter is connected to a series resonant circuit constituted by the applicator ICTP torch, a compensation capacitor and an impedance matching RF transformer. At the final, are presented the experimental results and the many tests achieved in laboratory as form to validate the proposed new technique

VCO Banda Larga Integrado para Receptor a Cinco Portas

This work presents an wideband ring VCO for cognitive radio five-port based receivers. A three-stage differential topology using transmission gate was adopted in order to maintain wide and linear tuning range and a low phase-noise. Monte-Carlo analysis were performed for phase-shift response of individual stages, which is an important figure of merit in five-port works. It was observed a fairly linear correlation between control voltage and oscillation frequency in the range between 200 MHz and 1800 MHz. The VCO was preliminarily designed for IBM 130nm CMOS technology

Uma fonte chaveada de 50kW com correção de fator de potência para alimentação de uma tocha de plasma Indutiva utilizando técnicas de controle digital

This work deals with the development of an experimental study on a power supply of high frequency that provides the toch plasmica to be implemented in PLASPETRO project, which consists of two static converters developed by using Insulated Gate Bipolar Transistor (IGBT). The drivers used to control these keys are triggered by Digital Signal Processor (DSP) through optical fibers to reduce problems with electromagnetic interference (EMI). The first stage consists of a pre-regulator in the form of an AC to DC converter with three-phase boost power factor correction which is the main theme of this work, while the second is the source of high frequency itself. A series-resonant inverter consists of four (4) cell inverters operating in a frequency around 115 kHz each one in soft switching mode, alternating itself to supply the load (plasma torch) an alternating current with a frequency of 450 kHz. The first stage has the function of providing the series-resonant inverter a DC voltage, with the value controlled from the power supply provided by the electrical system of the utility, and correct the power factor of the system as a whole. This level of DC bus voltage at the output of the first stage will be used to control the power transferred by the inverter to the load, and it may vary from 550 VDC to a maximum of 800 VDC. To control the voltage level of DC bus driver used a proportional integral (PI) controller and to achieve the unity power factor it was used two other proportional integral currents controllers. Computational simulations were performed to assist in sizing and forecasting performance. All the control and communications needed to stage supervisory were implemented on a DSP

Projeto em FPGA de um controlador unificado para correção de fator de potência em retificadores boost bidirecionais monofásicos

The use of Field Programmable Gate Array (FPGA) for development of digital control strategies for power electronics applications has aroused a growing interest of many researchers. This interest is due to the great advantages offered by FPGA, which include: lower design effort, high performance and highly flexible prototyping. This work proposes the development and implementation of an unified one-cycle controller for boost CFP rectifier based on FPGA. This controller can be applied to a total of twelve converters, six inverters and six rectifiers defined by four single phase VSI topologies and three voltage modulation types. The topologies considered in this work are: full-bridge, interleaved full-bridge, half-bridge and interleaved half-bridge. While modulations are classified in bipolar voltage modulation (BVM), unipolar voltage modulation (UVM) and clamped voltage modulation (CVM). The proposed project is developed and prototyped using tools Matlab/Simulink® together with the DSP Builder library provided by Altera®. The proposed controller was validated with simulation and experimental results

DC and AC side harmonics in CCC converters

The capacitor-commutated converter (CCC) has frequently been used in the conception of HVDC systems connected to busbars with low short circuit level. This alternative arrangement, in substitution to the conventional ones, guarantees less sensitive operational conditions to problems related with the commutation failure in the inverters besides supplying part of the reactive energy to be compensated. Studies related with its performance in steady and transient states have been presented in several works, however its behavior as harmonic source is still little explored. This work presents preliminary studies focusing the generation of characteristic harmonics by this type of converter. Subjects related with the amplification of the harmonic magnitudes are investigated and compared considering similar arrangements of conventional static converters (LCC) and CCC schemes. It is also analyzed the harmonic generation on the dc side of the installation and its influence on the ac side harmonics. The results are obtained from simulations in the time domain in PSpice environment and they clearly illustrate the operational differences between the L CC and the CCC schemes with regard to characteristic harmonic generation.

Low voltage analog synthesizer of orthogonal signals: A current-mode approach

An analog synthesizer of orthogonal signals for digital CMOS technology and 3V supply voltage is presented. The adaptive architecture accomplishes the synthesis of mutually orthogonal signal, such as trigonometric and polynomial basis. Experimental results using 0.35 mu m AMS CMOS process are presented for generation of the cosine and Legendre basis.

Low voltage analog synthesizer of orthogonal signals using current mode techniques

An analog synthesizer of orthogonal signals for digital CMOS technology and 3V supply voltage is presented. The adaptive architecture accomplishes the synthesis of mutually orthogonal signal, such as trigonometric and polynomial basis. Simulation results using 0.35 mu m AMS CMOS process are presented for generation of the cosine and Legendre basis.

Contribuições para a detecção e identificação de faltas em inversores Multiníveis

This work presents contributions in the detection and identication of faults in multilevel inverters through the study of the converters behavior under these operation conditions. Basically, the approached fault consists of an open-circuit in any switch of a three-level clamped diode inverter. The converter operation is characterized in the pre and post-fault states. A wave form behavior analysis of the pole voltage, phase current and dc-bus current is also done, which highlights characteristics that allow the detection of failure and, even, under favorable conditions, the identication of the faulty device. A compensation strategy of the approached fault (open-switch) is also investigated with the purpose of maintaining the driving system operational when a failure occurs. The proposed topology uses SCRs in parallel with the internal switches of the inverter, which allows, in some occasions, the full utilization of the dc-bus

Influence of cyclosporin A on quality of bone around integrated dental implants: a radiographic study in rabbits

To evaluate the influence of cyclosporin A (CsA) administration on bone around integrated dental implants assessed by a bone quality index and by quantitative subtraction radiography.A total of 36 machine surface commercial implants were placed in 18 adult rabbits. After a 3-month healing period without any disturbance, the animals were randomly divided into three groups of six animals each. Group A was sacrificed at this time. CsA was injected subcutaneously in an immunosuppressive dose of 10 mg/kg/day in a test group (Group T), and a Group B served as a control, receiving only vehicle. After 3 months of cyclosporin administration, the animals of both Groups B and T were sacrificed. Radiographs were obtained at implant surgery and at the day of sacrifice with a CMOS sensor. Bone quality around the implants was compared between the groups using a bone quality index and quantitative subtraction radiography.The bone analysis showed that in Group T, the bone quality changed dramatically from a dense cortical to a loose trabecular bone structure (P < 0.0001, chi(2) test) while in Groups A and B there were no significant differences. Quantitative digital subtraction radiography showed significantly (P < 0.05) lower gray shade values (radiographic density) in a region of bone formation around the implants in Group T (118 +/- 12) than in Groups A (161 +/- 6) and B (186 +/- 10).Within the limits of this study, CsA administration has a negative effect on the quality of bone around integrated dental implant.

A tunable triode-MOSFET transconductor and its application to g(m)-C filters

A linear, tunable CMOS transconductance stage is introduced. Drain voltage of the input transistor operating in triode region is settled by a regulation loop and a first-order linear relationship between g(m) and a de bias voltage is achieved. In addition to easy tuning, this technique offers circuit simplicity, wide dynamic range, high input and output impedances and low consumption. The transconductor is presented on both single-ended and fully-differential versions. A 3rd-order elliptical low-pass g(m)-C filter with a nominal roll-off frequency of 2MHz is used as one example for the many applications of the proposed transconductor. SPICE data describe circuits performances and filter tunabilily Passband is tuned at a rate of 2.36KHz/mV and good linearity is indicated by a 0.89% THD for an 800mV(p-p) balanced-driven input.

A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication

An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

On designing linear tunable high-Q OTA-C filters with low sensitivity

This paper discusses a design approach for a high-Q low-sensitivity OTA-C biquad bandpass section. An optimal relationship is established between transconductances defining the differencebeta - gamma in the Q-factor denominator, setting the Q-sensitivity to tuning voltages around unity. A 30-MHz filter was designed based on a 0.35 mum CMOS process and V-DD=3.3 V. A range of circuit simulation supports the theoretical analysis. Q-factor spans from 20.5 to 60, while ensuring filter stability along the tuning range. Although a triode-operating OTA is used, the procedure can be extended to other types of transconductor.