Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Low-cost digital signature architecture suitable for radio frequency identification tags

Continuing achievements in hardware technology are bringing ubiquitous computing closer to reality. The notion of a connected, interactive and autonomous environment is common to all sensor networks, biosystems and radio frequency identification (RFID) devices, and the emergence of significant deployments and sophisticated applications can be expected. However, as more information is collected and transmitted, security issues will become vital for such a fully connected environment. In this study the authors consider adding security features to low-cost devices such as RFID tags. In particular, the authors consider the implementation of a digital signature architecture that can be used for device authentication, to prevent tag cloning, and for data authentication to prevent transmission forgery. The scheme is built around the signature variant of the cryptoGPS identification scheme and the SHA-1 hash function. When implemented on 130 nm CMOS the full design uses 7494 gates and consumes 4.72 mu W of power, making it smaller and more power efficient than previous low-cost digital signature designs. The study also presents a low-cost SHA-1 hardware architecture which is the smallest standardised hash function design to date.

Anthropology, Socialist Prediction and William Morris’s Commonweal

In the late nineteenth century, a number of writers turned to anthropology to predict a socialist future. They included prominent revolutionary socialists: Friedrich Engels, William Morris and members of the Socialist League. Contextualising the appropriation of the anthropologist Lewis Henry Morgan by such readers, this article also pays particular attention to socialist popularisations of anthropology, particularly those by Morris and his fellow writers in his penny weekly, the Commonweal. Focusing on Morris’s articles on ancient society helps to illuminate his own understanding of history, art and socialism. It also sheds new light on his predictive fiction News from Nowhere, which was originally read alongside Commonweal non-fiction. Both, I will argue, encouraged readers to see the future in the struggles of the ancient past.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

Whose play is it anyway?: Theatre Studies, Translation Studies and translation for the stage

This article explores the historical neglect of translation as a consideration in the study and practice of theatre in the United States and Europe. While the study of literature is fairly strictly divided between English-language and Comparative Literature departments, theatre and drama have shown little concern about language as a barrier to reception of the dramatic text. Arguably, this discrepancy may be traced to a fundamental gap between the perceived status of the novel as a completed work of art and the playtext as work of art in progress, waiting to find its completion in performance.

An On Demand Queue Management Architecture for a Programmable Traffic Manager

A queue manager (QM) is a core traffic management (TM) function used to provide per-flow queuing in access andmetro networks; however current designs have limited scalability. An on-demand QM (OD-QM) which is part of a new modular field-programmable gate-array (FPGA)-based TM is presented that dynamically maps active flows to the available physical resources; its scalability is derived from exploiting the observation that there are only a few hundred active flows in a high speed network. Simulations with real traffic show that it is a scalable, cost-effective approach that enhances per-flow queuing performance, thereby allowing per-flow QM without the need for extra external memory at speeds up to 10 Gbps. It utilizes 2.3%–16.3% of a Xilinx XC5VSX50t FPGA and works at 111 MHz.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

Beyond the Sign. Henri Meschonnic's Poetics of Rhythm and Continuum. Towards an Anthropological Theory of Language

Basing the conception of language on the sign represents also an obstacle to the awareness of certain elements of human life, especially to a full understanding of what language or art do, Henri Meschonnic’s poetics of the continuum and of rhythm criticizes the sign based on Benveniste’s terms of rhythm and discourse, developing an anthropology of language. Rhythm, for Meschonnic, is no formal metrical but a semantic principle, each time unique and unforeseeable. As for Humboldt, his starting point is not the word but the ensemble of speech; language is not ergon but energeia. The poem then is not a literary form but a process of transformation that Meschonnic defines as the invention of a form of life by a form of language and vice versa. Thus a poem is a way of thinking and rhythm is form in movement. The particular subject of art and literature is consequently not the author but a process of subjectivation – this is the contrary of the conception of the sign. By demonstrating the limits of the sign, Meschonnic’s poetics attempts to thematize the intelligibility of presence. Art and literature raise our awareness of this element of human life we cannot grasp conceptually. This poetical thinking is a necessary counterforce against all institutionalization.

Evocative Listening : Mediated Practices in Everyday Life

The history of sonic arts is charged with transgressive practices that seek to expose the social, aural and cultural thresholds across various listening experiences, posing new questions in terms of the dialogue between listener and place. Recent work in sonic art exposes the need for an experiential understanding of listening that foregrounds the use of new personal technologies, environmental philosophy and the subject–object relationship. This paper aims to create a vocabulary that better contextualises recent installations and performances produced within the context of everyday life, by researchers and artists at the Sonic Arts Research Centre at Queen's University Belfast.

A Capabilities-Aware Framework for Using Computational Accelerators in Data-Intensive Computing

Multicore computational accelerators such as GPUs are now commodity components for highperformance computing at scale. While such accelerators have been studied in some detail as stand-alone computational engines, their integration in large-scale distributed systems raises new challenges and trade-offs. In this paper, we present an exploration of resource management alternatives for building asymmetric accelerator-based distributed systems. We present these alternatives in the context of a capabilities-aware framework for data-intensive computing, which uses an enhanced implementation of the MapReduce programming model for accelerator-based clusters, compared to the state of the art. The framework can transparently utilize heterogeneous accelerators for deriving high performance with low programming effort. Our work is the first to compare heterogeneous types of accelerators, GPUs and a Cell processors, in the same environment and the first to explore the trade-offs between compute-efficient and control-efficient accelerators on data-intensive systems. Our investigation shows that our framework scales well with the number of different compute nodes. Furthermore, it runs simultaneously on two different types of accelerators, successfully adapts to the resource capabilities, and performs 26.9% better on average than a static execution approach.

Efficient advanced encryption standard implementation using lookup and normal basis

A new type of advanced encryption standard (AES) implementation using a normal basis is presented. The method is based on a lookup technique that makes use of inversion and shift registers, which leads to a smaller size of lookup for the S-box than its corresponding implementations. The reduction in the lookup size is based on grouping sets of inverses into conjugate sets which in turn leads to a reduction in the number of lookup values. The above technique is implemented in a regular AES architecture using register files, which requires less interconnect and area and is suitable for security applications. The results of the implementation are competitive in throughput and area compared with the corresponding solutions in a polynomial basis.