Anankè et le symbolisme del l'architecture dans Notre-Dame de Paris de Victor Hugo

Esta dissertação propõe uma leitura textual do romance Notre-Dame de Paris, de Victor Hugo, a partir de algumas imagens singulares apresentadas nesta produção hugoliana. O objetivo deste percurso de pesquisa consiste em evidenciar a leitura simbólica da obra em questão, captada das relações da literatura com a arquitetura, configurada por algumas imagens nucleares, como Anankè, que assombra as figuras que povoam o romance, como o advento da imprensa, como a lucarna, como a cela do padre, entre outras. Sob este ângulo, acredita-se que o campo psicanalítico permite decifrar os efeitos do enigma e da fascinação produzidos pela obra hugoliana sobre o leitor. Nesse sentido, considera-se que o inconsciente representa o ponto de irradiação das pulsões, território que vai traduzir as relações espaciais da literatura com a arquitetura, enquanto expressões do simbólico. Desta maneira, o caminho de pesquisa se articula em três capítulos. Enquanto o primeiro, intitulado "Notre-Dame de Paris e a representação por imagens", visa a situar este percurso de pesquisa do ponto de vista do corpus teórico, representado, sobretudo, por Barthes e Blanchot, no que se refere à literatura, e por Freud, no que se refere à psicanálise; o segundo, intitulado "Notre-Dame de Paris e a crítica literária", procura apresentar uma leitura crítica baseada em quatro prefácios diferentes, de Notre-Dame de Paris: enfatizam o que seus autores destacam no contexto histórico que aparece escondido sob as imagens impostas pela escritura hugoliana; finalmente, o terceiro, intitulado "Imagens simbólicas de Notre-Dame de Paris", estabelece a leitura textual das imagens simbólicas que se produzem em Notre-Dame de Paris, intermediadas pelo cruzamento da literatura com a arquitetura.

DCE: the dynamic conditional execution in a multipath control independent architecture

This thesis presents DCE, or Dynamic Conditional Execution, as an alternative to reduce the cost of mispredicted branches. The basic idea is to fetch all paths produced by a branch that obey certain restrictions regarding complexity and size. As a result, a smaller number of predictions is performed, and therefore, a lesser number of branches are mispredicted. DCE fetches through selected branches avoiding disruptions in the fetch flow when these branches are fetched. Both paths of selected branches are executed but only the correct path commits. In this thesis we propose an architecture to execute multiple paths of selected branches. Branches are selected based on the size and other conditions. Simple and complex branches can be dynamically predicated without requiring a special instruction set nor special compiler optimizations. Furthermore, a technique to reduce part of the overhead generated by the execution of multiple paths is proposed. The performance achieved reaches levels of up to 12% when comparing a Local predictor used in DCE against a Global predictor used in the reference machine. When both machines use a Local predictor, the speedup is increased by an average of 3-3.5%.

RST: Reuse through Speculation on Traces

In this thesis, we present a novel approach to combine both reuse and prediction of dynamic sequences of instructions called Reuse through Speculation on Traces (RST). Our technique allows the dynamic identification of instruction traces that are redundant or predictable, and the reuse (speculative or not) of these traces. RST addresses the issue, present on Dynamic Trace Memoization (DTM), of traces not being reused because some of their inputs are not ready for the reuse test. These traces were measured to be 69% of all reusable traces in previous studies. One of the main advantages of RST over just combining a value prediction technique with an unrelated reuse technique is that RST does not require extra tables to store the values to be predicted. Applying reuse and value prediction in unrelated mechanisms but at the same time may require a prohibitive amount of storage in tables. In RST, the values are already stored in the Trace Memoization Table, and there is no extra cost in reading them if compared with a non-speculative trace reuse technique. . The input context of each trace (the input values of all instructions in the trace) already stores the values for the reuse test, which may also be used for prediction. Our main contributions include: (i) a speculative trace reuse framework that can be adapted to different processor architectures; (ii) specification of the modifications in a superscalar, superpipelined processor in order to implement our mechanism; (iii) study of implementation issues related to this architecture; (iv) study of the performance limits of our technique; (v) a performance study of a realistic, constrained implementation of RST; and (vi) simulation tools that can be used in other studies which represent a superscalar, superpipelined processor in detail. In a constrained architecture with realistic confidence, our RST technique is able to achieve average speedups (harmonic means) of 1.29 over the baseline architecture without reuse and 1.09 over a non-speculative trace reuse technique (DTM).

Reusing values in a dynamic conditional execution architecture

A Execução Condicional Dinâmica (DCE) é uma alternativa para redução dos custos relacionados a desvios previstos incorretamente. A idéia básica é buscar todos os fluxos produzidos por um desvio que obedecem algumas restrições relativas à complexidade e tamanho. Como conseqüência, um número menor de previsões é executado, e assim, um número mais baixo de desvios é incorretamente previsto. Contudo, tal como outras soluções multi-fluxo, o DCE requer uma estrutura de controle mais complexa. Na arquitetura DCE, é observado que várias réplicas da mesma instrução são despachadas para as unidades funcionais, bloqueando recursos que poderiam ser utilizados por outras instruções. Essas réplicas são geradas após o ponto de convergência dos diversos fluxos em execução e são necessárias para garantir a semântica correta entre instruções dependentes de dados. Além disso, o DCE continua produzindo réplicas até que o desvio que gerou os fluxos seja resolvido. Assim, uma seção completa do código pode ser replicado, reduzindo o desempenho. Uma alternativa natural para esse problema é reusar essas seções (ou traços) que são replicadas. O objetivo desse trabalho é analisar e avaliar a efetividade do reuso de valores na arquitetura DCE. Como será apresentado, o princípio do reuso, em diferentes granularidades, pode reduzir efetivamente o problema das réplicas e levar a aumentos de desempenho.

Nesting architecture and population structure of the fungus-growing ant Cyphomyrmex transversus (Formicidae: Myrmicinae: Attini) in the Brazilian coastal zone of Ilheus, Bahia

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Metodologia para adaptação de microarquiteturas microprogramadas soft-core à uma ISA padrão: estudo do impacto sobre a complexidade de hardware para o padrão MIPS

In academia, it is common to create didactic processors, facing practical disciplines in the area of Hardware Computer and can be used as subjects in software platforms, operating systems and compilers. Often, these processors are described without ISA standard, which requires the creation of compilers and other basic software to provide the hardware / software interface and hinder their integration with other processors and devices. Using reconfigurable devices described in a HDL language allows the creation or modification of any microarchitecture component, leading to alteration of the functional units of data path processor as well as the state machine that implements the control unit even as new needs arise. In particular, processors RISP enable modification of machine instructions, allowing entering or modifying instructions, and may even adapt to a new architecture. This work, as the object of study addressing educational soft-core processors described in VHDL, from a proposed methodology and its application on two processors with different complexity levels, shows that it s possible to tailor processors for a standard ISA without causing an increase in the level hardware complexity, ie without significant increase in chip area, while its level of performance in the application execution remains unchanged or is enhanced. The implementations also allow us to say that besides being possible to replace the architecture of a processor without changing its organization, RISP processor can switch between different instruction sets, which can be expanded to toggle between different ISAs, allowing a single processor become adaptive hybrid architecture, which can be used in embedded systems and heterogeneous multiprocessor environments

Implementação de processador banda base ofdma para downlink lte em fpga

This work treats of an implementation OFDMA baseband processor in hardware for LTE Downlink. The LTE or Long Term Evolution consist the last stage of development of the technology called 3G (Mobile System Third Generation) which offers an increasing in data rate and more efficiency and flexibility in transmission with application of advanced antennas and multiple carriers techniques. This technology applies in your physical layer the OFDMA technical (Orthogonal Frequency Division Multiple Access) for generation of signals and mapping of physical resources in downlink and has as base theoretical to OFDM multiple carriers technique (Orthogonal Frequency Division Multiplexing). With recent completion of LTE specifications, different hardware solutions have been developed, mainly, to the level symbol processing where the implementation of OFDMA processor in base band is commonly considered, because it is also considered a basic architecture of others important applications. For implementation of processor, the reconfigurable hardware offered by devices as FPGA are considered which shares not only to meet the high requirements of flexibility and adaptability of LTE as well as offers possibility of an implementation quick and efficient. The implementation of processor in reconfigurable hardware meets the specifications of LTE physical layer as well as have the flexibility necessary for to meet others standards and application which use OFDMA processor as basic architecture for your systems. The results obtained through of simulation and verification functional system approval the functionality and flexibility of processor implemented

The nest architecture of the ant, Pheidole oxyops Forel, 1908 (Hymenoptera : Formicidae)

Pheidole oxyops builds subterranean nests, with an external architecture that is distinctive and easily recognizable by its wide and specific entrance hole, measuring up to 12.2 cm in diameter, denoting a pitfall-trap. In order to study the nests'internal architecture, seven nests were excavated; four were identified with neutral talc, while the others were cast in cement and then excavated. Measurements were made in order to gain a better understanding of their structures, and a photographic documentation was obtained as well. The excavations revealed that the nests are perpendicular relative to the ground, beginning with a cylindrical channel with a mean length of 13.5 cm, containing irregular formations, and whose diameter becomes progressively narrower until the first chamber is formed. As the channel continues, dish-like chambers appear, interconnected by channels that become progressively narrower and longer, while the chambers are arranged at greater distances from each other as nest depth increases. Both channels and chambers are located on the vertical projection of the entrance hole. Nests may reach a depth of up to 5.09 m, with a number of chambers ranging between 4 and 14.

Internal Architecture and Population Size of Acromyrmex subterraneus molestans (Hymenoptera, Formicidae) Nests: Comparison Between a Rural and an Urban Area

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Iron phthalocyanine in non-aqueous medium forming layer-by-layer films: growth mechanism, molecular architecture and applications

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Molecular architecture of thin films fabricated via physical vapor deposition and containing a poly(azo)urethane

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Optimized architecture for Tyrosinase-containing Langmuir-Blodgett films to detect pyrogallol

The control of molecular architectures has been a key factor for the use of Langmuir-Blodgett (LB) films in biosensors, especially because biomolecules can be immobilized with preserved activity. In this paper we investigated the incorporation of tyrosinase (Tyr) in mixed Langmuir films of arachidic acid (AA) and a lutetium bisphthalocyanine (LuPc2), which is confirmed by a large expansion in the surface pressure isotherm. These mixed films of AA-LuPc2 + Tyr could be transferred onto ITO and Pt electrodes as indicated by FTIR and electrochemical measurements, and there was no need for crosslinking of the enzyme molecules to preserve their activity. Significantly, the activity of the immobilised Tyr was considerably higher than in previous work in the literature, which allowed Tyr-containing LB films to be used as highly sensitive voltammetric sensors to detect pyrogallol. Linear responses have been found up to 400 mu M, with a detection limit of 4.87 x 10(-2) mu M (n = 4) and a sensitivity of 1.54 mu A mu M-1 cm(-2). In addition, the Hill coefficient (h = 1.27) indicates cooperation with LuPc2 that also acts as a catalyst. The enhanced performance of the LB-based biosensor resulted therefore from a preserved activity of Tyr combined with the catalytic activity of LuPc2, in a strategy that can be extended to other enzymes and analytes upon varying the LB film architecture.