936 resultados para Maximum Power Point Tracking


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This paper presents the design and implementation of a differential 4-way power-combining amplifier operating at E-band. The proposed 4-way power combiner (4WPC) facilitates short interconnects to the PA cells, thereby resulting in reduced loss. Simple C-L-C and L-C networks are deployed in order to compensate inductive loading due to the routing lines that would otherwise introduce mismatch and subsequently increase overall loss. Realized in SiGe technology, the PA prototype delivered 13.2 dBm output-referred 1-dB compression point and 14.3 dBm saturated output power when operated from a single 3.3 V DC supply at 75 GHz.

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This paper investigates the impacts of offshore wind power forecast error on the operation and management of a pool-based electricity market in 2050. The impact from offshore wind power forecast errors of up to 2000 MW on system generation costs, emission costs, dispatch-down of wind, number of start-ups and system marginal price are analysed. The main findings of this research are an increase in system marginal prices of approximately 1% for every percentage point rise in the offshore wind power forecast error regardless of the average forecast error sign. If offshore wind power generates less than forecasted (−13%) generation costs and system marginal prices increases by 10%. However, if offshore wind power generates more than forecasted (4%) the generation costs decrease yet the system marginal prices increase by 3%. The dispatch down of large quantities of wind power highlights the need for flexible interconnector capacity. From a system operator's perspective it is more beneficial when scheduling wind ahead of the trading period to forecast less wind than will be generated.

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We consider the uplink of massive multicell multiple-input multiple-output systems, where the base stations (BSs), equipped with massive arrays, serve simultaneously several terminals in the same frequency band. We assume that the BS estimates the channel from uplink training, and then uses the maximum ratio combining technique to detect the signals transmitted from all terminals in its own cell. We propose an optimal resource allocation scheme which jointly selects the training duration, training signal power, and data signal power in order to maximize the sum spectral efficiency, for a given total energy budget spent in a coherence interval. Numerical results verify the benefits of the optimal resource allocation scheme. Furthermore, we show that more training signal power should be used at low signal-to-noise ratio (SNRs), and vice versa at high SNRs. Interestingly, for the entire SNR regime, the optimal training duration is equal to the number of terminals.

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In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

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This paper presents a surrogate-model based optimization of a doubly-fed induction generator (DFIG) machine winding design for maximizing power yield. Based on site-specific wind profile data and the machine’s previous operational performance, the DFIG’s stator and rotor windings are optimized to match the maximum efficiency with operating conditions for rewinding purposes. The particle swarm optimization (PSO)-based surrogate optimization techniques are used in conjunction with the finite element method (FEM) to optimize the machine design utilizing the limited available information for the site-specific wind profile and generator operating conditions. A response surface method in the surrogate model is developed to formulate the design objectives and constraints. Besides, the machine tests and efficiency calculations follow IEEE standard 112-B. Numerical and experimental results validate the effectiveness of the proposed technologies.

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Power has become a key constraint in current nanoscale integrated circuit design due to the increasing demands for mobile computing and a low carbon economy. As an emerging technology, an inexact circuit design offers a promising approach to significantly reduce both dynamic and static power dissipation for error tolerant applications. Although fixed-point arithmetic circuits have been studied in terms of inexact computing, floating-point arithmetic circuits have not been fully considered although require more power. In this paper, the first inexact floating-point adder is designed and applied to high dynamic range (HDR) image processing. Inexact floating-point adders are proposed by approximately designing an exponent subtractor and mantissa adder. Related logic operations including normalization and rounding modules are also considered in terms of inexact computing. Two HDR images are processed using the proposed inexact floating-point adders to show the validity of the inexact design. HDR-VDP is used as a metric to measure the subjective results of the image addition. Significant improvements have been achieved in terms of area, delay and power consumption. Comparison results show that the proposed inexact floating-point adders can improve power consumption and the power-delay product by 29.98% and 39.60%, respectively.

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Power has become a key constraint in nanoscale inte-grated circuit design due to the increasing demands for mobile computing and higher integration density. As an emerging compu-tational paradigm, an inexact circuit offers a promising approach to significantly reduce both dynamic and static power dissipation for error-tolerant applications. In this paper, an inexact floating-point adder is proposed by approximately designing an exponent sub-tractor and mantissa adder. Related operations such as normaliza-tion and rounding are also dealt with in terms of inexact computing. An upper bound error analysis for the average case is presented to guide the inexact design; it shows that the inexact floating-point adder design is dependent on the application data range. High dynamic range images are then processed using the proposed inexact floating-point adders to show the validity of the inexact design; comparison results show that the proposed inexact floating-point adders can improve the power consumption and power-delay product by 29.98% and 39.60%, respectively.

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Embedded memories account for a large fraction of the overall silicon area and power consumption in modern SoC(s). While embedded memories are typically realized with SRAM, alternative solutions, such as embedded dynamic memories (eDRAM), can provide higher density and/or reduced power consumption. One major challenge that impedes the widespread adoption of eDRAM is that they require frequent refreshes potentially reducing the availability of the memory in periods of high activity and also consuming significant amount of power due to such frequent refreshes. Reducing the refresh rate while on one hand can reduce the power overhead, if not performed in a timely manner, can cause some cells to lose their content potentially resulting in memory errors. In this paper, we consider extending the refresh period of gain-cell based dynamic memories beyond the worst-case point of failure, assuming that the resulting errors can be tolerated when the use-cases are in the domain of inherently error-resilient applications. For example, we observe that for various data mining applications, a large number of memory failures can be accepted with tolerable imprecision in output quality. In particular, our results indicate that by allowing as many as 177 errors in a 16 kB memory, the maximum loss in output quality is 11%. We use this failure limit to study the impact of relaxing reliability constraints on memory availability and retention power for different technologies.

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A new approach to determine the local boundary of voltage stability region in a cut-set power space (CVSR) is presented. Power flow tracing is first used to determine the generator-load pair most sensitive to each branch in the interface. The generator-load pairs are then used to realize accurate small disturbances by controlling the branch power flow in increasing and decreasing directions to obtain new equilibrium points around the initial equilibrium point. And, continuous power flow is used starting from such new points to get the corresponding critical points around the initial critical point on the CVSR boundary. Then a hyperplane cross the initial critical point can be calculated by solving a set of linear algebraic equations. Finally, the presented method is validated by some systems, including New England 39-bus system, IEEE 118-bus system, and EPRI-1000 bus system. It can be revealed that the method is computationally more efficient and has less approximation error. It provides a useful approach for power system online voltage stability monitoring and assessment. This work is supported by National Natural Science Foundation of China (No. 50707019), Special Fund of the National Basic Research Program of China (No. 2009CB219701), Foundation for the Author of National Excellent Doctoral Dissertation of PR China (No. 200439), Tianjin Municipal Science and Technology Development Program (No. 09JCZDJC25000), National Major Project of Scientific and Technical Supporting Programs of China During the 11th Five-year Plan Period (No. 2006BAJ03A06). ©2009 State Grid Electric Power Research Institute Press.

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Rationale
Previous research on attention bias in nondependent social drinkers has focused on adult samples with limited focus on the presence of attention bias for alcohol cues in adolescent social drinkers.
Objectives
The aim of this study was to examine the presence of alcohol attention bias in adolescents and the relationship of this cognitive bias to alcohol use and alcohol-related expectancies.
Methods
Attention bias in adolescent social drinkers and abstainers was measured using an eye tracker during exposure to alcohol and neutral cues. Questionnaires measured alcohol use and explicit alcohol expectancies.
Results
Adolescent social drinkers spent significantly more time fixating to alcohol stimuli compared to controls. Total fixation time to alcohol stimuli varied in accordance with level of alcohol consumption and was significantly associated with more positive alcohol expectancies. No evidence for automatic orienting to alcohol stimuli was found in adolescent social drinkers.
Conclusion
Attention bias in adolescent social drinkers appears to be underpinned by controlled attention suggesting that whilst participants in this study displayed alcohol attention bias comparable to that reported in adult studies, the bias has not developed to the point of automaticity. Initial fixations appeared to be driven by alternative attentional processes which are discussed further.

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With the increasing utilization of electric vehicles (EVs), transportation systems and electrical power systems are becoming increasingly coupled. However, the interaction between these two kinds of systems are not well captured, especially from the perspective of transportation systems. This paper studies the reliability of integrated transportation and electrical power system (ITES). A bidirectional EV charging control strategy is first demonstrated to model the interaction between the two systems. Thereafter, a simplified transportation system model is developed, whose high efficiency makes the reliability assessment of the ITES realizable with an acceptable accuracy. Novel transportation system reliability indices are then defined from the view point of EV’s driver. Based on the charging control model and the transportation simulation method, a daily periodic quasi sequential reliability assessment method is proposed for the ITES system. Case studies based on RBTS system demonstrate that bidirectional charging controls of EVs will benefit the reliability of power systems, while decrease the reliability of EVs travelling. Also, the optimal control strategy can be obtained based on the proposed method. Finally, case studies are performed based on a large scale test system to verify the practicability of the proposed method.

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The results in this paper are based on a data set containing system demand, wind generation and CO2 emission between Jan 2010 and Sep 2013. The data was recorded at 15 minute intervals and reflects the macroscopic operation of the Republic of Ireland's electrical grid. The data was analyzed by investigating how daily wind generation effected daily CO2 emission across multiple days with equivalent daily demand. A figure for wind turbine efficiency was determined by dividing the CO2 mitigation potential of wind power by the CO2 intensity of the grid; both in units of Tonnes of CO2 per MWh. The yearly wind power efficiency appears to have increased by 5.6% per year, now standing around 90%. Over the four years significant regularity was observed in the profiles of wind turbine efficiency against daily demand. It appears that the efficiency profile has moved in recent years so that maximum efficiency coincides with most frequent demand.

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This paper presents a new variant of broadband Doherty power amplifier that employs a novel output combiner. A new parameter ∝ is introduced to permit a generalized analysis of the recently reported Parallel Doherty power amplifier (PDPA),and hence offer design flexibility. The circuit prototype of the new DPA fabricated using GaN devices exhibits maximum drain efficiency of 85% at 43-dBm peak power and 63% at 6-dB backoff power (BOP). Measured drain efficiency of >60% at peak power across 500-MHz frequency range and >50% at 6-dB BOP across 480-MHz frequency range were achieved, confirming the  theoretical wideband characteristics of the new DPA.

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The development of 5G enabling technologies brings new challenges to the design of power amplifiers (PAs). In particular, there is a strong demand for low-cost, nonlinear PAs which, however, introduce nonlinear distortions. On the other hand, contemporary expensive PAs show great power efficiency in their nonlinear region. Inspired by this trade-off between nonlinearity distortions and efficiency, finding an optimal operating point is highly desirable. Hence, it is first necessary to fully understand how and how much the performance of multiple-input multiple-output (MIMO) systems deteriorates with PA nonlinearities. In this paper, we first reduce the ergodic achievable rate (EAR) optimization from a power allocation to a power control problem with only one optimization variable, i.e. total input power. Then, we develop a closed-form expression for the EAR, where this variable is fixed. Since this expression is intractable for further analysis, two simple lower bounds and one upper bound are proposed. These bounds enable us to find the best input power and approach the channel capacity. Finally, our simulation results evaluate the EAR of MIMO channels in the presence of nonlinearities. An important observation is that the MIMO performance can be significantly degraded if we utilize the whole power budget.