It Had to Be You:Clarinet and Computer

World Premiere by Esther Lamneck

Audley's Light:Flute and Computer

Performance by Elizabeth McNutt

Evaluating a Computer System that Converses Fluently with People

The SAL system embodies a new kind of human-computer interaction, where a person and a computer carry out a fluent, emotionally coloured conversation. Because that kind of capability is new, evaluating systems that have it is a new challenge. This paper outlines techniques that have been developed to evaluate SAL interactions, and uses the case to highlight the range of variables that become relevant in dealing with systems of this order of complexity.

A Sensitivity Approach for Eliminating Clashes from Computer Aided Design Model Assemblies

Clashes occur when components in an assembly unintentionally violate others. If clashes are not identified and designed out before manufacture, product function will be reduced or substantial cost will be incurred in rework. This paper introduces a novel approach for eliminating clashes by identifying which parameters defining the part features in a computer aided design (CAD) assembly need to change and by how much. Sensitivities are calculated for each parameter defining the part and the assembly as the change in clash volume due to a change in each parameter value. These sensitivities give an indication of important parameters and are used to predict the optimum combination of changes in each parameter to eliminate the clash. Consideration is given to the fact that it is sometimes preferable to modify some components in an assembly rather than others and that some components in an assembly cannot be modified as the designer does not have control over their shape. Successful elimination of clashes has been demonstrated in a number of example assemblies.

It Had to Be You Performance at NYCEMF 2014:for Clarinet and Computer

Concert 15: 3:30-5:30 PM: Playhouse

Danny Saul, Glitches/Trajectories
Ethan Greene, Lissajous
Kyong Mee Choi, Ceaseless Cease
Thomas Beverly, Ocotillo

intermission

Paul Wilson, It Had to be You
Kwangrae Kim, Sound Drawing
Steven Kemper, Mythical Spaces
David Durant, FAJI

Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.