Verification and FPGA circuits of a block-2 fast path-based predictor

This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one mis-prediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.

FPGA organization for the fast path-based neural branch predictor

This paper develops cycle-level FPGA circuits of an organization for a fast path-based neural branch predictor Our results suggest that practical sizes of prediction tables are limited to around 32 KB to 64 KB in current FPGA technology due mainly to FPGA area of logic resources to maintain the tables. However the predictor scales well in terms of prediction speed. Table sizes alone should not be used as the only metric for hardware budget when comparing neural-based predictor to predictors of totally different organizations. This paper also gives early evidence to shift the attention on to the recovery from mis-prediction latency rather than on prediction latency as the most critical factor impacting accuracy of predictions for this class of branch predictors.

Experiences applying OVM 2.0 to an 8B/10B RTL design

The SystemVerilog implementation of the Open Verification Methodology (OVM) is exercised on an 8b/10b RTL open core design in the hope of being a simple yet complete exercise to expose the key features of OVM. Emphasis is put onto the actual usage of the verification components rather than a complete verification flow aiming at being of help to readers unfamiliar with OVM seeking to apply the methodology to their own designs. A link that takes you to the complete code is given to reinforce this aim. We found the methodology easy to use but intimidating at first glance specially for someone with little experience in object oriented programming. However it is clear to see the flexibility, portability and reusability of verification code once you manage to give some first steps.

Preliminary results from a real time control system using optical information

Successful results from training an adaptive controller to use optical information to balance an inverted pendulum are presented in comparison to the training requirements using traditional controller inputs. Results from research into the psychology of the sense of balance in humans are presented as the motivation for the investigation of this new type of controller. The simulated model of the inverted pendulum and the virtual reality environments used to provide the optical input are described The successful introduction of optical information is found to require the preservation of at least two of the traditional input types and entail increased training time for the adaptive controller and reduced performance (measured as the time the pendulum remains upright).

Results of applying sensor fusion to a control system using optic flow

The results from applying a sensor fusion process to an adaptive controller used to balance all inverted pendulum axe presented. The goal of the sensor fusion process was to replace some of the four mechanical measurements, which are known to be sufficient inputs for a linear state feedback controller to balance the system, with optic flow variables. Results from research into the psychology of the sense of balance in humans were the motivation for the investigation of this new type of controller input. The simulated model of the inverted pendulum and the virtual reality environments used to provide the optical input are described. The successful introduction of optical information is found to require the preservation of at least two of the traditional input types and entail increased training till-le for the adaptive controller and reduced performance (measured as the time the pendulum remains upright)

Efficient FPGA-based regular expression pattern matching

An approach to the automatic generation of efficient Field Programmable Gate Arrays (FPGAs) circuits for the Regular Expression-based (RegEx) Pattern Matching problems is presented. Using a novel design strategy, as proposed, circuits that are highly area-and-time-efficient can be automatically generated for arbitrary sets of regular expressions. This makes the technique suitable for applications that must handle very large sets of patterns at high speed, such as in the network security and intrusion detection application domains. We have combined several existing techniques to optimise our solution for such domains and proposed the way the whole process of dynamic generation of FPGAs for RegEX pattern matching could be automated efficiently.

Real-time context-aware network security policy enforcement system (RC-NSPES)

The major technical objectives of the RC-NSPES are to provide a framework for the concurrent operation of reactive and pro-active security functions to deliver efficient and optimised intrusion detection schemes as well as enhanced and highly correlated rule sets for more effective alerts management and root-cause analysis. The design and implementation of the RC-NSPES solution includes a number of innovative features in terms of real-time programmable embedded hardware (FPGA) deployment as well as in the integrated management station. These have been devised so as to deliver enhanced detection of attacks and contextualised alerts against threats that can arise from both the network layer and the application layer protocols. The resulting architecture represents an efficient and effective framework for the future deployment of network security systems.

'Flat phase' PID controllers

Flat Phase PID Controllers have the property that the phase of the transfer function round the associated feedback loop is constant or flat around the design frequency, with the aim that the phase margin and overshoot to a step response is unaffected when the gain of the device under control changes. Such designs have been achieved using Bode Integrals and by ensuring the phase is the same at two frequencies. This paper extends the ‘two frequency’ controller and describes a novel three frequency controller. The different design strategies arc compared.

Impedance control of redundant drive joints with double actuation

This paper proposes impedance control of redundant drive joints with double actuation (RDJ-DA) to produce compliant motions with the future goal of higher bandwidth. First, to reduce joint inertia, a double-input-single-output mechanism with one internal degree of freedom (DOF) is presented as part of the basic structure of the RDJ-DA. Next, the basic structure of RDJ-DA is further explained and its dynamics and statics are derived. Then, the impedance control scheme of RDJ-DA to produce compliant motions is proposed and the validity of the proposed controller is investigated using numerical examples.

A practical method for testing high-speed networking hardware architectures

This paper deals with the key issues encountered in testing during the development of high-speed networking hardware systems by documenting a practical method for "real-life like" testing. The proposed method is empowered by modern and commonly available Field Programmable Gate Array (FPGA) technology. Innovative application of standard FPGA blocks in combination with reconfigurability are used as a back-bone of the method. A detailed elaboration of the method is given so as to serve as a general reference. The method is fully characterised and compared to alternatives through a case study proving it to be the most efficient and effective one at a reasonable cost.

Multiple-model fault tolerant control of terminal unites of HVAC Systems

In this work, a fault-tolerant control scheme is applied to a air handling unit of a heating, ventilation and air-conditioning system. Using the multiple-model approach it is possible to identify faults and to control the system under faulty and normal conditions in an effective way. Using well known techniques to model and control the process, this work focuses on the importance of the cost function in the fault detection and its influence on the reconfigurable controller. Experimental results show how the control of the terminal unit is affected in the presence a fault, and how the recuperation and reconfiguration of the control action is able to deal with the effects of faults.

A clocking technique for FPGA pipelined designs

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. (C) 2004 Elsevier B.V. All rights reserved.

Switching curve control of functional electrical stimulation assisted rowing exercise in paraplegia

An indoor rowing machine has been modified for functional electrical stimulation (FES) assisted rowing exercise in paraplegia. To perform the rowing manoeuvre successfully, however, the voluntarily controlled upper body movements must be co-ordinated with the movements of the electrically stimulated paralysed legs. To achieve such co-ordination, an automatic FES controller was developed that employs two levels of hierarchy. At the upper level, a finite state controller identifies the state or phase of the rowing cycle and activates the appropriate lower-level controller, in which electrical stimulation to the paralysed leg muscles is applied with reference to switching curves representing the desired seat velocity as a function of the seat position. In a pilot study, the hierarchical control of FES rowing was shown to be intuitive, reliable and easy to use. Compared with open-loop control of stimulation, all three variants of the closed-loop switching curve controllers used less muscle stimulation per rowing cycle (73% of the open-loop control on average). Further, the closed-loop controller that used switching curves derived from normal rowing kinematics used the lowest muscle stimulation (65% of the open-loop control) and was the most convenient to use for the client.

Input constraints handling in an MPC/feedback linearization scheme

The combination of model predictive control based on linear models (MPC) with feedback linearization (FL) has attracted interest for a number of years, giving rise to MPC+FL control schemes. An important advantage of such schemes is that feedback linearizable plants can be controlled with a linear predictive controller with a fixed model. Handling input constraints within such schemes is difficult since simple bound contraints on the input become state dependent because of the nonlinear transformation introduced by feedback linearization. This paper introduces a technique for handling input constraints within a real time MPC/FL scheme, where the plant model employed is a class of dynamic neural networks. The technique is based on a simple affine transformation of the feasible area. A simulated case study is presented to illustrate the use and benefits of the technique.

Synapsing variable length crossover: An algorithm for crossing and comparing variable length genomes

The Synapsing Variable Length Crossover (SVLC) algorithm provides a biologically inspired method for performing meaningful crossover between variable length genomes. In addition to providing a rationale for variable length crossover it also provides a genotypic similarity metric for variable length genomes enabling standard niche formation techniques to be used with variable length genomes. Unlike other variable length crossover techniques which consider genomes to be rigid inflexible arrays and where some or all of the crossover points are randomly selected, the SVLC algorithm considers genomes to be flexible and chooses non-random crossover points based on the common parental sequence similarity. The SVLC Algorithm recurrently "glues" or synapses homogenous genetic sub-sequences together. This is done in such a way that common parental sequences are automatically preserved in the offspring with only the genetic differences being exchanged or removed, independent of the length of such differences. In a variable length test problem the SVLC algorithm is shown to outperform current variable length crossover techniques. The SVLC algorithm is also shown to work in a more realistic robot neural network controller evolution application.