Oromotor dysfunction and communication impairments in children with cerebral palsy: a Register study

Aim  To report the prevalence, clinical associations, and trends over time of oromotor dysfunction and communication impairments in children with cerebral palsy (CP).

Method  Multiple sources of ascertainment were used and children followed up with a standardized assessment including motor speech problems, swallowing/chewing difficulties, excessive drooling, and communication impairments at age 5 years.

Results  A total of 1357 children born between 1980 and 2001 were studied (781 males, 576 females; median age 5y 11mo, interquartile range 3–9y; unilateral spastic CP, n=447; bilateral spastic CP, n=496; other, n=112; Gross Motor Function Classification System [GMFCS] level: I, 181; II, 563; III, 123; IV, 82; IV, 276). Of those with ‘early-onset’ CP (n=1268), 36% had motor speech problems, 21% had swallowing/chewing difficulties, 22% had excessive drooling, and 42% had communication impairments (excluding articulation defects). All impairments were significantly related to poorer gross motor function and intellectual impairment. In addition, motor speech problems were related to clinical subtype; swallowing/chewing problems and communication impairments to early mortality; and communication impairments to the presence of seizures. Of those with CP in GMFCS levels IV to V, a significant proportion showed a decline in the rate of motor speech impairment (p=0.008) and excessive drooling (p=0.009) over time.

Interpretation  These impairments are common in children with CP and are associated with poorer gross motor function and intellectual impairment.

Sub-mm wet etched linear to circular polarization fss based polarization converters

This communication investigates the potential for fabrication of micromachined silicon sub-millimeter wave periodic arrays of freestanding slot frequency selective surfaces (FSS) using wet etch KOH technology. The vehicle for this is an FSS for generating circularly polarized signals from an incident linearly polarized signal at normal incidence to the structure. Principal issues and fabrication processes involved from the initial design of the core FSS structures to be made and tested through to their final testing are addressed. Measured and simulated results for crossed and ring slot element shapes in single and double layer polarization convertor structures are presented for sub-mm wave operation. It is shown that 3 dB axial ratio (AR) bandwidths of 21% can be achieved with the one layer perforated screen design and that the rate of change is lower than the double layer structures. An insertion loss of 1.1 dB can be achieved for the split circular ring double layer periodic array. These results are shown to be compatible with the more specialized fabrication equipment dry reactive ion etching approach previously used for the construction of this type of structure. © 2011 IEEE.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.