Optically programmable logic cells as basic units for transmission and synchronization of chaotic signals

We proposed an optical communications system, based on a digital chaotic signal where the synchronization of chaos was the main objective, in some previous papers. In this paper we will extend this work. A way to add the digital data signal to be transmitted onto the chaotic signal and its correct reception, is the main objective. We report some methods to study the main characteristics of the resulting signal. The main problem with any real system is the presence of some retard between the times than the signal is generated at the emitter at the time when this signal is received. Any system using chaotic signals as a method to encrypt need to have the same characteristics in emitter and receiver. It is because that, this control of time is needed. A method to control, in real time the chaotic signals, is reported.

Photonic switching architectures with logic cells

Possible switching architectures, with Optically Programmable Logic Cells - OPLCs - will be reported in this paper. These basic units, previously employed by us for some other applications mainly in optical computing, will be employed as main elements to switch optical communications signals. The main aspect to be considered is that because the nternal components of these cells have nonlinear behaviors, namely either pure bistable or SEED-like properties, several are the possibilities to be obtained. Moreover, because their properties are dependent, under certain condition, of the signal wavelength, they are apt to be employed in WDM systems and the final result will depend on the orresponding optical signal frequency. We will give special emphasis to the case where self-routing is achieved, namely to structures of the Batcher or Banyan type. In these cases, as it will be shown, there is the possibility to route any packet input to a certain direction according to its first bits. The number of possible outputs gives the number of bits needed to route signals. An advantage of this configuration is that a very versatile behavior may be allowed. The main one is the possibility to obtain configurations with different kinds of behavior, namely, Strictly Nonblocking, Wide-Sense Nonblocking or Rearrangeably Nonblocking as well as to eliminate switching conflicts at a certain intermediate stages.

Coder/decoder with an optical programmable logic cell

A major research area is the representation of knowledge for a given application in a compact manner such that desired information relating to this knowledge is easily recoverable. A complicated procedure may be required to recover the information from the stored representation and convert it back to usable form. Coder/decoder are the devices dedicated to that task. In this paper the capabilities that an Optical Programmable Logic Cell offers as a basic building block for coding and decoding are analyzed. We have previously published an Optically Programmable Logic Cells (OPLC), for applications as a chaotic generator or as basic element for optical computing. In optical computing previous studies these cells have been analyzed as full-adder units, being this element a basic component for the arithmetic logic structure in computing. Another application of this unit is reported in this paper. Coder and decoder are basic elements in computers, for example, in connections between processors and memory addressing. Moreover, another main application is the generation of signals for machine controlling from a certain instruction. In this paper we describe the way to obtain a coder/decoder with the OPLC and which type of applications may be the best suitable for this type of cell.

Logic cells as basic structures to add/drop WDM information signals

Nowadays, in order to take advantage of fiber optic bandwidth, any optical communications system tends to be WDM. The way to extract a channel, characterized by a wavelength, from the optical fiber is to filter the specific wavelength. This gives the systems a low degree of freedom due to the fact of the static character of most of the employed devices. In this paper we will present a different way to extract channels from an optical fiber with WDM transmission. The employed method is based on an Optically Programmable Logic Cells (OPLC) previously published by us, for other applications as a chaotic generator or as basic element for optical computing. In this paper we will describe the configuration of the OPLC to be employed as a dropping device. It acts as a filter because it will extract the data carried by a concrete wavelength. It does depend, internally, on the wavelength. We will show how the intensity of the signal is able to select the chosen information from the line. It will be also demonstrated that a new idea of redundant information it is the way of selecting the concrete wavelength. As a matter of fact this idea is apparently the only way to use the OPLC as a dropping device. Moreover, based on these concepts, a similar way to route signals to different routes is reported. The basis is the use of photonic switching configurations, namely Batcher or Bayan structures, where the unit switching cells are the above indicated OPLCs.

Boolean logic device done with DFB laser diode

We present simulation results on how power output-input characteristic Instability in Distributed FeedBack -DFB semiconductor laser diode SLA can be employed to implemented Boolean logic device. Two configurations of DFB Laser diode under external optical injection, either in the transmission or in the reflective mode of operation, is used to implement different Optical Logic Cells (OLCs), called the Q- and the P-Device OLCs. The external optical injection correspond to two inputs data plus a cw control signal that allows to choose the Boolean logic function to be implement. DFB laser diode parameters are choosing to obtain an output-input characteristic with the values desired. The desired values are mainly the on-off contrast and switching power, conforming shape of hysteretic cycle. Two DFB lasers in cascade, one working in transmission operation and the other one in reflective operation, allows designing an inputoutput characteristic based on the same respond of a self-electrooptic effect device is obtained. Input power for a bit'T' is 35 uW(70uW) and a bit "0" is zero for all the Boolean function to be execute. Device control signal range to choose the logic function is 0-140 uW (280 uW). Q-device (P-device)

Dynamic control of a reconfigurable stair-climbing mobility system

Electric-powered wheelchairs improve the mobility of people with physical disabilities, but the problem to deal with certain architectural barriers has not been resolved satisfactorily. In order to solve this problem, a stair-climbing mobility system (SCMS) was developed. This paper presents a practical dynamic control system that allows the SCMS to exhibit a successful climbing process when faced with typical architectural barriers such as curbs, ramps, or staircases. The implemented control system depicts high simplicity, computational efficiency, and the possibility of an easy implementation in a microprocessor-/microcontroller-based system. Finally, experiments are included to support theoretical results.

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

Towards an abstract domain for resource analysis of logic programs using sized types

We present a novel general resource analysis for logic programs based on sized types.Sized types are representations that incorporate structural (shape) information and allow expressing both lower and upper bounds on the size of a set of terms and their subterms at any position and depth. They also allow relating the sizes of terms and subterms occurring at different argument positions in logic predicates. Using these sized types, the resource analysis can infer both lower and upper bounds on the resources used by all the procedures in a program as functions on input term (and subterm) sizes, overcoming limitations of existing analyses and enhancing their precision. Our new resource analysis has been developed within the abstract interpretation framework, as an extension of the sized types abstract domain, and has been integrated into the Ciao preprocessor, CiaoPP. The abstract domain operations are integrated with the setting up and solving of recurrence equations for both, inferring size and resource usage functions. We show that the analysis is an improvement over the previous resource analysis present in CiaoPP and compares well in power to state of the art systems.

Sized Type Analysis for Logic Programs (Technical Communication)

We present a novel analysis for relating the sizes of terms and subterms occurring at diferent argument positions in logic predicates. We extend and enrich the concept of sized type as a representation that incorporates structural (shape) information and allows expressing both lower and upper bounds on the size of a set of terms and their subterms at any position and depth. For example, expressing bounds on the length of lists of numbers, together with bounds on the values of all of their elements. The analysis is developed using abstract interpretation and the novel abstract operations are based on setting up and solving recurrence relations between sized types. It has been integrated, together with novel resource usage and cardinality analyses, in the abstract interpretation framework in the Ciao preprocessor, CiaoPP, in order to assess both the accuracy of the new size analysis and its usefulness in the resource usage estimation application. We show that the proposed sized types are a substantial improvement over the previous size analyses present in CiaoPP, and also benefit the resource analysis considerably, allowing the inference of equal or better bounds than comparable state of the art systems.

Design techniques for xilinx virtex FPGA configuration memory scrubbers

SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.

Floating-point exponentiation units for reconfigurable computing

The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function xy as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

A self-adaptive image processing application based on evolvable and scalable hardware

Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications.

UAS See-and-Avoid Strategy using a Fuzzy Logic Controller Optimized by Cross-Entropy in Scaling Factors and Membership Functions

This work aims to develop a novel Cross-Entropy (CE) optimization-based fuzzy controller for Unmanned Aerial Monocular Vision-IMU System (UAMVIS) to solve the seeand- avoid problem using its accurate autonomous localization information. The function of this fuzzy controller is regulating the heading of this system to avoid the obstacle, e.g. wall. In the Matlab Simulink-based training stages, the Scaling Factor (SF) is adjusted according to the specified task firstly, and then the Membership Function (MF) is tuned based on the optimized Scaling Factor to further improve the collison avoidance performance. After obtained the optimal SF and MF, 64% of rules has been reduced (from 125 rules to 45 rules), and a large number of real flight tests with a quadcopter have been done. The experimental results show that this approach precisely navigates the system to avoid the obstacle. To our best knowledge, this is the first work to present the optimized fuzzy controller for UAMVIS using Cross-Entropy method in Scaling Factors and Membership Functions optimization.

Explointing FPGA block memories for protected cryptographic implementations

Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security.

Contribution to active multi-beam reconfigurable antennas for L and S bands

La presente tesis doctoral con título "Contribution to Active Multi-Beam Reconfigurable Antennas for L and S Bands" ha sido desarrollada por el investigador ingeniero de telecomunicación estudiante de doctorado Javier García-Gasco Trujillo en el Grupo de Radiación del Departamento de Señales, Sistemas y Radiocomunicaciones de la ETSI de Telecomunicación de la Universidad Politécnica de Madrid bajo la dirección de los doctores Manuel Sierra Pérez y José Manuel Fernández González. Durante décadas, el desarrollo de antenas de apuntamiento electrónico ha estado limitado al área militar. Su alto coste y su gran complejidad eran los mayores obstáculos que frenaban la introducción de esta tecnología en aplicaciones comerciales de gran escala. La reciente aparición de componentes de estado sólido prácticos, fiables, y de bajo coste ha roto la barrera del coste y ha reducido la complejidad, haciendo que las antenas reconfigurables de apuntamiento electrónico sean una opción viable en un futuro cercano. De esta manera, las antenas phased array podrían llegar a ser la joya de la corona que permitan alcanzar los futuros retos presentes en los sistemas de comunicaciones tanto civiles como militares. Así pues, ahora es el momento de investigar en el desarrollo de antenas de apuntamiento electrónico de bajo coste, donde los nuevos componentes de estado sólido comerciales forman el núcleo duro de la arquitectura. De esta forma, el estudio e implementación de estos arrays de antenas activas de apuntamiento electrónico capaces de controlar la fase y amplitud de las distintas señales implicadas es uno de los grandes retos de nuestro tiempo. Esta tesis se enfrenta a este desafío, proponiendo novedosas redes de apuntamiento electrónico e innovadores módulos de transmisión/recepción (T/R) utilizando componentes de estado sólido de bajo coste, que podrán integrar asequibles antenas activas reconfigurables multihaz en bandas L y S. En la primera parte de la tesis se realiza una descripción del estado del arte de las antenas phased array, incluyendo su base teórica y sus ventajas competitivas. Debido a que las contribuciones obtenidas en la presente tesis han sido realizadas dentro de distintos proyectos de investigación, donde se han manejada antenas de simple/doble polarización circular y simple/doble banda de trabajo, se describen detenidamente los dos proyectos más relevantes de la investigación: el radar de basura espacial de la Agencia Espacial Europea (ESA), Space Situational Awareness (SSA); y la estación base de seguimiento y control de satélites de órbita baja, GEOdesic Dome Array (GEODA). Sin lugar a dudas, los dispositivos desfasadores son uno de los componentes clave en el diseño de antenas phased arrays. Recientemente se ha observado una gran variación en el precio final de estos dispositivos, llegando en ocasiones a límites inasequibles. Así pues, se han propuesto distintas técnicas de conformación de haz alternativas a la utilización de componentes desfasadores comerciales: el desfasador de líneas conmutadas, la red de haz conmutado, y una novedosa red desfasadora divisora/combinadora de potencia. Para mostrar un uso práctico de las mismas, se ha propuesto el uso de las tres alternativas para el caso práctico del subarray de cinco elementos de la celda GEODA-SARAS. Tras dicho estudio se obtiene que la novedosa red desfasadora divisora/combinadora de potencia propuesta es la que mejor relación comportamiento/coste presenta. Para verificar su correcto funcionamiento se construye y mide los dos bloques principales de los que está compuesta la red total, comprobando que en efecto la red responde según lo esperado. La estructura más simple que permite realizar un barrido plano es el array triangular de tres elementos. Se ha realizado el diseño de una nueva red multihaz que es capaz de proporcionar tres haces ortogonales en un ángulo de elevación _0 y un haz adicional en la dirección broadside utilizando el mencionado array triangular de tres elementos como antena. En primer lugar se realizar una breve introducción al estado del arte de las redes clásicas multihaz. Así mismo se comentan innovadores diseños de redes multihaz sin pérdidas. El estudio da paso a las redes disipativas, de tal forma que se analiza su base matemática y se muestran distintas aplicaciones en arrays triangulares de tres elementos. Finalmente, la novedosa red básica propuesta se presenta, mostrando simulaciones y medidas de la misma para el caso prácticoo de GEODA. También se ha diseñado, construido y medido una red compuesta por dos redes básicas complementarias capaz de proporcionar seis haces cuasi-ortogonales en una dirección _0 con dos haces superpuestos en broadside. La red propuesta queda totalmente validada con la fabricación y medida de estos con prototipos. Las cadenas de RF de los módulos T/R de la nueva antena GEODA-SARAS no son algo trivial. Con el fin de mostrar el desarrollo de una cadena compleja con una gran densidad de componentes de estado sólido, se presenta una descripción detallada de los distintos componentes que integran las cadenas de RF tanto en transmisión como en recepción de la nueva antena GEODA-SARAS. Tras presentar las especificaciones de la antena GEODA-SARA y su diagrama de bloques esquemático se describen los dos bloques principales de las cadenas de RF: la celda de cinco elementos, y el módulo de conversión de panel. De la misma manera también se presentará el módulo de calibración integrado dentro de los dos bloques principales. Para comprobar que el funcionamiento esperado de la placa es el adecuado, se realizará un análisis que tratará entre otros datos: la potencia máxima en la entrada del transmisor (comprobando la saturación de la cadena), señal de recepción mínima y máxima (verificando el rango de sensibilidad requerido), y el factor G/T (cumpliendo la especificación necesaria). Así mismo se mostrará un breve estudio del efecto de la cuantificación de la fase en el conformado de haz de RF. Los estudios muestran que la composición de las cadenas de RF permite el cumplimiento de las especificaciones necesarias. Finalmente la tesis muestra las conclusiones globales del trabajo realizado y las líneas futuras a seguir para continuar con esta línea de investigación. ABSTRACT This PhD thesis named "Contribution to Active Multi-Beam Reconfigurable Antennas for L and S Bands", has been written by the Electrical Engineer MSc. researcher Javier García-Gasco Trujillo in the Grupo de Radiación of the Departamento de Señales, Sistemas y Radiocomunicaciones from the ETSI de Telecomunicación of the Universidad Politécnica de Madrid. For decades, the implementation of electronically steerable phased array antennas was confined to the military area. Their high cost and complexity were the major obstacles to introduce this technology in large scale commercial applications. The recent emergence of new practical, low-cost, and highly reliable solid state devices; breaks the barrier of cost and reduces the complexity, making active phased arrays a viable future option. Thus, phased array antennas could be the crown jewel that allow to meet the future challenges in military and civilian communication systems. Now is time to deploy low-cost phased array antennas, where newly commercial components form the core of the architecture. Therefore, the study and implementation of these novel low-cost and highly efficient solid state phased array blocks capable of controlling signal phase/amplitude accurately is one of the great challenges of our time. This thesis faces this challenge, proposing innovative electronic beam steering networks and transmitter/ receiver (T/R) modules using affordable solid state components, which could integrate fair reconfigurable phased array antennas working in L and S bands. In the first part of the thesis, a description of the state of art of phased array antennas, including their fundamentals and their competitive advantages, is presented. Since thesis contributions have been carried out for different research projects, where antennas with single/double circular polarization and single/double working frequency bands have been examined, frameworks of the two more important projects are detailed: the Space Situational Awareness (SSA) programme from the European Space Agency (ESA), and the GEOdesic Dome Array (GEODA) project from ISDEFE-INSA and the ESA. Undoubtedly, phase shifter devices are one of the key components of phased array antennas. Recent years have witnessed wide fluctuations in commercial phase shifter prices, which sometimes led to unaffordable limit. Several RF steering technique alternatives to the commercial phase shifters are proposed, summarized, and compared: the switched line phase shifter, the switched-beam network, and the novel phase shifter power splitter/combiner network. In order to show a practical use of the three different techniques, the five element GEODA-SARAS subarray is proposed as a real case of study. Finally, a practical study of a newly phase shifter power splitter/combiner network for a subarray of five radiating elements with triangular distribution is shown. Measurements of the two different phase shifter power splitter/combiner prototypes integrating the whole network are also depicted, demonstrating their proper performance. A triangular cell of three radiating elements is the simplest way to obtain a planar scanner. A new multibeam network configuration that provides three orthogonal beams in a desired _0 elevation angle and an extra one in the broadside steering direction for a triangular array of three radiating elements is introduced. Firstly, a short introduction to the state of art of classical multi-beam networks is presented. Lossless network analysis, including original lossless network designs, are also commented. General dissipative network theory as well as applications for array antennas of three radiating elements are depicted. The proposed final basic multi-beam network are simulated, built and measured to the GEODA cell practical case. A combined network that provides six orthogonal beams in a desired _0 elevation angle and a double seventh one in the broadside direction by using two complementary proposed basic networks will be shown. Measurements of the whole system will be also depicted, verifying the expected behavior. GEODA-SARAS T/R module RF chains are not a trivial design. A thorough description of all the components compounding GEODA-SARAS T/R module RF chains is presented. After presenting the general specifications of the GEODA-SARAS antenna and its block diagrams; two main blocks of the RF chains, the five element cell and the panel conversion module, are depicted and analyzed. Calibration module integrated within the two main blocks are also depicted. Signal flow throw the system analyzing critical situations such as maximum transmitted power (testing the chain unsaturation), minimum and maximum receiving signal (verifying sensitivity range), maximum receiver interference signals (assuring a proper reception), and G/T factor (fulfilling the technical specification) are evaluated. Phase quantization error effects are also listed. Finally, the manuscript contains the conclusions drawn of the present research and the future work.