Internal quantum efficiency analysis of solar cell by genetic algorithm

To investigate factors limiting the performance of a GaAs solar cell, genetic algorithm is employed to fit the experimentally measured internal quantum efficiency (IQE) in the full spectra range. The device parameters such as diffusion lengths and surface recombination velocities are extracted. Electron beam induced current (EBIC) is performed in the base region of the cell with obtained diffusion length agreeing with the fit result. The advantage of genetic algorithm is illustrated.

EFFECTS OF 1-MEV-ELECTRON IRRADIATION ON A-SI SOLAR-CELLS

In this report we present the effects of 1 MeV-electron irradiation on i a-Si:H films and solar cells. It is observed that in the dose range of 1.4-8.4 x 10(15) cm(-2) the defect creation has not reached its saturation level and the metastable defects caused by the irradiation cannot be completely removed by a two hour annealing at 200 degrees C for i a-Si:H films or at 130 degrees C for a-Si:H solar cells. The results may be understood in terms of a model based on two kinds of metastable defects created by 1 MeV-electron irradiation.

A COMPARATIVELY LOW-QUALITY SILICON MATERIAL IMPROVED FOR SOLAR-CELL FABRICATION

A comparatively low-quality silicon wafer (with a purity of almost-equal-to 99.9%) was adopted to form a silicon-on-defect-layer (SODL) structure featuring improved crystalline silicon near the defect layer (DL) by means of proton implantation and subsequent annealing. Thus, the SODL technique provides an opportunity to enable low-quality silicon wafers to be used for fabrication of low-cost solar cells.

35-PERCENT EFFICIENT NONCONCENTRATING NOVEL SILICON SOLAR-CELL

An energy conversion efficiency of 35% was obtained at 1-sun, air mass 1.5 for a novel silicon cell having an area of 2.3 X 2.3 mm2 . cell. The critical feature of the cell structure is the inclusion of local defect layers near a p-n junction. The local defect layers were proven to hold the key to achieving the exceptionally high efficiency of the novel cell fabricated via noncomplex processing.

METASTABLE DEFECT IN AMORPHOUS-SILICON SOLAR-CELLS INVESTIGATED BY JUNCTION RECOVERY TECHNIQUE

The effect of metastable defects caused by light soaking and carrier injection on the transport of carriers in undoped a-Si:H has been investigated by a junction recovery technique. The experiments show that after light soaking or carrier injection the product of mu-p-tau-p decreases, but no detectable change in the distribution of shallow valence band tail states was found.

Microcrystalline silicon films and tandem solar cells prepared by triode PECVD

This paper investigates the effects of the diphasic structure on the optoelectronic properties of hydrogenated microcrystalline silicon (mu c-Si:H) films prepared in a triode three-chamber plasma-enhanced chemical vapor deposition (PECVD) system. The influences of boron-compensation doping on the dark-and photo-conductivity of mu c-Si:H films are also described. A tandem solar cell with an entirely mu c-Si:H p-i-n bottom cell and an a-Si:H top cell has been prepared with an initial conversion efficiency of 8.91% (0.126 cm(2), AM1.5, 100 mW/cm(2)).

Polycrystalline silicon thin films and solar cells prepared by rapid thermal CVD

Polycrystalline silicon (poly-Si) films(similar to 10 mu m) were grown from dichlorosilane by a rapid thermal chemical vapor deposition (RTCVD) technique, with a growth rate up to 100 Angstrom/s at the substrate temperature (T-s) of 1030 degrees C. The average grain size and carrier mobility of the films were found to be dependent on the substrate temperature and material. By using the poly-Si films, the first model pn(+) junction solar cell without anti-reflecting (AR) coating has been prepared on an unpolished heavily phosphorus-doped Si wafer, with an energy conversion efficiency of 4.54% (AM 1.5, 100 mW/cm(2), 1 cm(2)).

The cost estimate for a novel cheap solar cell

The estimate for the lowest cost of SODL (silicon on defect layer) solar cell is made according to the price standard of present market. The estimate shows that the PV (photovoltaics) energy costs can be reduced from today's 25-30 cents/(kW h) to 7-8 cents/(kW h) which is comparable with the present cost of electricity generated by traditional energy sources such as fossil and petroleum fuels. The PV energy costs could be reduced to a value lower than 7-8 cents(kW h) by developing SODL technology. The SODL solar cell manufacture featuring simple processes is suitable to large scale automated assembly lines with high yield of large area cells. Some new ideas are suggested, favoring the further reduction in the cost of commercial solar cells.

High efficiency AlxGa1-xAs/GaAs solar cells: Fabrication, irradiation and annealing effect

High efficiency AlxGa1-xAs/GaAs heteroface solar cells have been fabricated by an improved multi-wafer squeezing graphite boat liquid phase epitaxy (LPE) technique, which enables simultaneous growth of twenty 2.3 X 2.3cm(2) epilayers in one run. A total area conversion efficiency of 17.33% is exhibited (1sun, AM0, 2.0 x 2.0cm(2)). The shallow junction cell shows more resistance to 1 MeV electron radiation than the deep one. After isochronal or isothermal annealing the density and the number of deep level traps induced by irradiation are reduced effectively for the solar cells with deep junction and bombardment under high electron fluences.

Structure and device characteristics of AlxGa1-xAs/GaAs solar cells

AlGa1-xAs/GaAs heterostructures have been grown by two different liquid phase epitaxy (LPE) modes, i.e. the supercooled and melt-etch methods, for the fabrication of highly efficient solar cells. Typical structural characteristics observed under a transmission electron microscope (TEM), an Auger energy spectrometer (AES) and corresponding device parameters were presented. The results indicated that the P+PNN+ configuration grown by the melt-etch method could be used to produce high performance, large area solar cells with effectively reducing the defects of the substrate and improving the minority carrier collection by forming a compositionally graded region in the window layer.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.