Comparative switching behaviour of silicon transistors and practical silicon carbide transistors

The motivation for our work is to identify a space for silicon carbide (SiC) devices in the silicon (Si) world. This paper presents a detailed experimental investigation of the switching behaviour of silicon and silicon carbide transistors (a JFET and a cascode device comprising a Si-MOSFET and a SiC-JFET). The experimental method is based on a clamped inductive load chopper circuit that puts considerable stress on the device and increases the transient power dissipation. A precise comparison of switching behaviour of Si and SiC devices on similar terms is the novelty of our work. The cascode is found to be an attractive fast switching device, capable of operating in two different configurations whose switching equivalent circuits are proposed here. The effect of limited dv/dt of the Si-MOSFET on the switching of the SiC-JFET in a cascode is also critically analysed.

Parameter extraction and calorimetric validation for a silicon carbide jfet pspice model

This paper focuses on the PSpice model of SiC-JFET element inside a SiCED cascode device. The device model parameters are extracted from the I-V and C-V characterization curves. In order to validate the model, an inductive test rig circuit is designed and tested. The switching loss is estimated both using oscilloscope and calorimeter. These results are found to be in good agreement with the simulated results.

High-efficiency InGaN/GaN quantum well structures on large area silicon substrates

The growth techniques which have enabled the realization of InGaN-based multi-quantum-well (MQW) structures with high internal quantum efficiencies (IQE) on 150mm (6-in.) silicon substrates are reviewed. InGaN/GaN MQWs are deposited onto GaN templates on large-area (111) silicon substrates, using AlGaN strain-mediating interlayers to inhibit thermal-induced cracking and wafer-bowing, and using a SiN x interlayer to reduce threading dislocation densities in the active region of the MQW structure. MQWs with high IQE approaching 60% have been demonstrated. Atomic resolution electron microscopy and EELS analysis have been used to study the nature of the important interface between the Si(111) substrate and the AlN nucleation layer. We demonstrate an amorphous SiN x interlayer at the interface about 2nm wide, which does not, however, prevent good epitaxy of the AlN on the Si(111) substrate. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

TRANSIENT SCANNING ELECTRON BEAM ANNEALING METHODS USED TO STUDY DIFFUSION AND DEFECTS IN IMPLANTED SILICON.

Rapid thermal annealing of arsenic and boron difluoride implants, such as those used for source/drain regions in CMOS, has been carried out using a scanning electron beam annealer, as part of a study of transient diffusion effects. Three types of e-beam anneal have been performed, with peak temperatures in the range 900 -1200 degree C; the normal isothermal e-beam anneals, together with sub-second fast anneals and 'dual-pulse' anneals, in which the sample undergoes an isothermal pre-anneal followed by rapid heating to the required anneal temperature is less than 0. 5s. The diffusion occuring during these anneal cycles has been modelled using SPS-1D, an implant and diffusion modelling program developed by one of the authors. This has been modified to incorporate simulated temperature vs. time cycles for the anneals. Results are presented applying the usual equilibrium clustering model, a transient point-defect enhancement to the diffusivity proposed recently by Fair and a new dynamic clustering model for arsenic. Good agreement with SIMS measurements is obtained using the dynamic clustering model, without recourse to a transient defect model.

Zinc oxide nanowire based hydrogen sensor on SOI CMOS platform

Here we report on the successful low-temperature growth of zinc oxide nanowires (ZnONWs) on silicon-on-insulator (SOI) CMOS micro-hotplates and their response, at different operating temperatures, to hydrogen in air. The SOI micro-hotplates were fabricated in a commercial CMOS foundry followed by a deep reactive ion etch (DRIE) in a MEMS foundry to form ultra-low power membranes. The micro-hotplates comprise p+ silicon micro-heaters and interdigitated metal electrodes (measuring the change in resistance of the gas sensitive nanomaterial). The ZnONWs were grown as a post-CMOS process onto the hotplates using a CMOS friendly hydrothermal method. The ZnONWs showed a good response to 500 to 5000 ppm of hydrogen in air. We believe that the integration of ZnONWs with a MEMS platform results in a low power, low cost, hydrogen sensor that would be suitable for handheld battery-operated gas sensors. © 2011 Published by Elsevier Ltd.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.

Ferroelectric liquid crystal over silicon devices

Over the past 20 years, ferroelectric liquid crystal over silicon (FLCOS) devices have made a wide impact on applications as diverse as optical correlation and holographic projection. To cover the entire gamut of this technology would be difficult and long winded; hence, this paper describes the significant developments of FLCOS within the Engineering Department at the University of Cambridge.The purpose of this paper is to highlight the key issues in fabricating silicon backplane spatial light modulators (SLMs) and to indicate ways in which the technology can be fabricated using cheap, low-density production and manufacturability. Three main devices have been fabricated as part of several research programmes and are documented in this paper. The fast bitplane SLM and the reconfigurable optical switches for aerospace and telecommunications systems (ROSES) SLM will form the basis of a case study to outline the overall processes involved. There is a great deal of commonality in the fabrication processes for all three devices, which indicates their potential strength and demonstrates that these processes can be made independent of the SLMs that are being assembled. What is described is a generic process that can be applied to any silicon backplane SLM on a die-by-die basis. There are hundreds of factors that can affect the yield in a manufacturing process and the purpose of a good process design procedure is to minimise these factors. One of the most important features in designing a process is fabrication experience, as so many of the lessons in this business can only be learned this way. We are working with the advantage of knowing the mistakes already made in the flat panel display industry, but we are also faced with the fact that those mistakes took many years and many millions of dollars to make.The fabrication process developed here originates and adapts earlier processes from various groups around the world. There are also a few totally new processes that have now been adopted by others in the field. Many, such as the gluing process, are still on-going and have to be worked on more before they will fully suit 'manufacturability'. © 2012 Copyright Taylor and Francis Group, LLC.

Stress-induced domain dynamics and phase transitions in epitaxially grown VO₂ nanowires.

We demonstrate that surface stresses in epitaxially grown VO₂ nanowires (NWs) have a strong effect on the appearance and stability of intermediate insulating M₂ phases, as well as the spatial distribution of insulating and metallic domains during structural phase transitions. During the transition from an insulating M1 phase to a metallic R phase, the coexistence of insulating M₁ and M₂ phases with the absence of a metallic R phase was observed at atmospheric pressure. In addition, we show that, for a VO₂ NW without the presence of an epitaxial interface, surface stresses dominantly lead to spatially inhomogeneous phase transitions between insulating and metallic phases. In contrast, for a VO₂ NW with the presence of an epitaxial interface, the strong epitaxial interface interaction leads to additional stresses resulting in uniformly alternating insulating and metallic domains along the NW length.